blob: b53fbc5161c520730b39a37c4235dc9aed20c3ce [file] [log] [blame]
Masahiro Yamada53f6ec62014-11-26 18:33:59 +09001/*
2 * Device Tree Source for UniPhier PH1-Pro4 SoC
3 *
4 * Copyright (C) 2014 Panasonic Corporation
5 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 compatible = "panasonic,ph1-pro4";
14
15 cpus {
16 #size-cells = <0>;
17 #address-cells = <1>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 };
24
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
32 soc {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
Masahiro Yamadaf8cd9b02014-11-26 18:34:00 +090037
38 uart0: serial@54006800 {
39 compatible = "panasonic,uniphier-uart";
40 status = "disabled";
41 reg = <0x54006800 0x20>;
42 clock-frequency = <73728000>;
43 };
44
45 uart1: serial@54006900 {
46 compatible = "panasonic,uniphier-uart";
47 status = "disabled";
48 reg = <0x54006900 0x20>;
49 clock-frequency = <73728000>;
50 };
51
52 uart2: serial@54006a00 {
53 compatible = "panasonic,uniphier-uart";
54 status = "disabled";
55 reg = <0x54006a00 0x20>;
56 clock-frequency = <73728000>;
57 };
58
59 uart3: serial@54006b00 {
60 compatible = "panasonic,uniphier-uart";
61 status = "disabled";
62 reg = <0x54006b00 0x20>;
63 clock-frequency = <73728000>;
64 };
Masahiro Yamada53f6ec62014-11-26 18:33:59 +090065 };
66};