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git01.mediatek.com / filogic / uboot / f8bf0e997b3a255cb57aa68d35adb8964981a237 / . / drivers / reset / rst-rk3576.c
blob: a6b83a2fd74a2d4217f16979204b09444bdf47be [file] [log] [blame]
Elaine Zhangf8bf0e92025-04-15 23:51:19 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 * Author: Detlev Casanova <detlev.casanova@collabora.com>
6 * Based on Sebastian Reichel's implementation for RK3588
7 */
8
9#include <dm.h>
10#include <asm/arch-rockchip/clock.h>
11#include <dt-bindings/reset/rockchip,rk3576-cru.h>
12
13/* 0x27200000 + 0x0A00 */
14#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + (reg) * 16 + (bit))
15/* 0x27208000 + 0x0A00 */
16#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000 * 4 + (reg) * 16 + (bit))
17/* 0x27210000 + 0x0A00 */
18#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + (reg) * 16 + (bit))
19/* 0x27220000 + 0x0A00 */
20#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + (reg) * 16 + (bit))
21
22/* mapping table for reset ID to register offset */
23static const int rk3576_register_offset[] = {
24 /* SOFTRST_CON01 */
25 RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
26 RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5),
27 RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6),
28 RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
29 RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14),
30
31 /* SOFTRST_CON02 */
32 RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
33 RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
34
35 /* SOFTRST_CON06 */
36 RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
37
38 /* SOFTRST_CON07 */
39 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
40 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
41 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
42 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
43 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
44 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
45 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
46 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10),
48 RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
49 RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
50 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
51 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
52
53 /* SOFTRST_CON08 */
54 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
55 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1),
56 RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5),
57 RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6),
58 RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8),
59 RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10),
60 RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
61 RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14),
62
63 /* SOFTRST_CON09 */
64 RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
65 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
66 RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
67 RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
68 RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
69 RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
70 RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
71 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
72 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
73 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
74 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
75
76 /* SOFTRST_CON11 */
77 RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
78 RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4),
79 RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5),
80 RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6),
81 RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
82 RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
83 RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
84 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
85 RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
86 RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14),
87 RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
88
89 /* SOFTRST_CON12 */
90 RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
91 RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
92 RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
93 RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3),
94 RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4),
95 RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5),
96 RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6),
97 RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7),
98 RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8),
99 RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
100 RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10),
101 RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11),
102 RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12),
103 RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13),
104 RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14),
105 RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15),
106
107 /* SOFTRST_CON13 */
108 RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0),
109 RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1),
110 RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
111 RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3),
112 RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4),
113 RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6),
114 RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
115 RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8),
116 RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
117 RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10),
118 RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11),
119 RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12),
120 RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13),
121 RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14),
122 RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15),
123
124 /* SOFTRST_CON14 */
125 RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0),
126 RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1),
127 RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
128 RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3),
129 RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4),
130 RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5),
131 RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6),
132 RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
133 RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12),
134 RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15),
135
136 /* SOFTRST_CON15 */
137 RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
138 RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5),
139 RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8),
140 RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
141 RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10),
142 RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
143 RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13),
144 RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14),
145 RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15),
146
147 /* SOFTRST_CON16 */
148 RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0),
149 RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1),
150 RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2),
151 RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3),
152 RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4),
153 RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5),
154 RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6),
155 RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7),
156 RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8),
157 RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
158 RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10),
159 RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11),
160
161 /* SOFTRST_CON17 */
162 RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3),
163 RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4),
164 RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6),
165 RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7),
166 RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8),
167 RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
168 RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10),
169 RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11),
170 RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12),
171 RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13),
172 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15),
173
174 /* SOFTRST_CON18 */
175 RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0),
176 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1),
177 RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2),
178 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3),
179 RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4),
180 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5),
181 RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6),
182 RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7),
183 RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8),
184 RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
185 RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11),
186 RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12),
187 RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13),
188 RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14),
189 RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15),
190
191 /* SOFTRST_CON19 */
192 RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0),
193 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1),
194 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2),
195 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3),
196 RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4),
197 RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5),
198 RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7),
199 RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
200 RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11),
201 RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12),
202 RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13),
203
204 /* SOFTRST_CON20 */
205 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0),
206 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1),
207 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3),
208 RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4),
209 RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5),
210 RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8),
211 RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
212 RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12),
213 RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13),
214
215 /* SOFTRST_CON21 */
216 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1),
217 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2),
218 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3),
219 RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4),
220 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5),
221 RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6),
222 RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10),
223 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13),
224 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14),
225 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15),
226
227 /* SOFTRST_CON22 */
228 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0),
229 RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1),
230 RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2),
231 RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3),
232 RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4),
233 RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6),
234 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
235 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10),
236 RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12),
237 RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13),
238 RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14),
239 RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15),
240
241 /* SOFTRST_CON23 */
242 RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1),
243 RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2),
244 RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4),
245 RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5),
246 RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6),
247 RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7),
248 RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8),
249 RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
250 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11),
251
252 /* SOFTRST_CON25 */
253 RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1),
254 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2),
255 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3),
256 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4),
257 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5),
258 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6),
259
260 /* SOFTRST_CON26 */
261 RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1),
262 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2),
263 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3),
264 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4),
265 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5),
266 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6),
267
268 /* SOFTRST_CON27 */
269 RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0),
270 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1),
271
272 /* SOFTRST_CON28 */
273 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
274 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11),
275 RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12),
276
277 /* SOFTRST_CON29 */
278 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0),
279 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2),
280 RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3),
281
282 /* SOFTRST_CON31 */
283 RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0),
284 RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1),
285 RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
286 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10),
287 RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12),
288 RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13),
289 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14),
290 RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15),
291
292 /* SOFTRST_CON32 */
293 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0),
294 RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1),
295 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
296 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3),
297 RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4),
298 RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6),
299 RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
300 RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8),
301 RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11),
302 RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12),
303 RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13),
304
305 /* SOFTRST_CON33 */
306 RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2),
307 RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3),
308 RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6),
309 RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7),
310 RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8),
311 RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
312 RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10),
313 RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11),
314 RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12),
315
316 /* SOFTRST_CON34 */
317 RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1),
318 RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5),
319 RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
320 RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13),
321 RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15),
322
323 /* SOFTRST_CON35 */
324 RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3),
325 RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11),
326 RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13),
327 RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14),
328
329 /* SOFTRST_CON36 */
330 RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0),
331 RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7),
332 RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
333
334 /* SOFTRST_CON37 */
335 RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0),
336 RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1),
337 RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2),
338 RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3),
339 RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4),
340 RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5),
341 RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6),
342 RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7),
343
344 /* SOFTRST_CON40 */
345 RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2),
346 RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3),
347
348 /* SOFTRST_CON42 */
349 RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3),
350 RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4),
351 RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5),
352 RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6),
353 RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7),
354 RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8),
355 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
356 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10),
357 RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12),
358
359 /* SOFTRST_CON43 */
360 RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2),
361 RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3),
362 RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4),
363 RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6),
364 RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7),
365 RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8),
366 RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10),
367 RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11),
368 RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13),
369
370 /* SOFTRST_CON45 */
371 RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3),
372 RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5),
373 RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6),
374 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8),
375 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
376
377 /* SOFTRST_CON47 */
378 RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3),
379 RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4),
380 RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5),
381 RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10),
382 RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12),
383 RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13),
384 RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15),
385
386 /* SOFTRST_CON48 */
387 RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0),
388 RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1),
389 RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2),
390
391 /* SOFTRST_CON49 */
392 RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6),
393 RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
394 RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10),
395 RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
396 RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12),
397 RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13),
398 RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14),
399 RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15),
400
401 /* SOFTRST_CON50 */
402 RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0),
403 RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1),
404 RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2),
405 RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3),
406 RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4),
407 RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5),
408 RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6),
409 RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7),
410 RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10),
411 RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11),
412 RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12),
413
414 /* SOFTRST_CON51 */
415 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2),
416 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3),
417 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4),
418 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5),
419 RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6),
420
421 /* SOFTRST_CON53 */
422 RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3),
423 RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4),
424 RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5),
425 RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6),
426 RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7),
427 RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8),
428 RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10),
429 RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11),
430
431 /* SOFTRST_CON54 */
432 RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1),
433 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4),
434 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5),
435 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6),
436 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7),
437 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8),
438
439 /* SOFTRST_CON59 */
440 RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0),
441 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1),
442 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2),
443 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3),
444 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4),
445 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5),
446
447 /* SOFTRST_CON61 */
448 RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4),
449 RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5),
450 RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6),
451 RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7),
452 RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8),
453 RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
454 RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13),
455
456 /* SOFTRST_CON62 */
457 RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0),
458 RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1),
459 RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2),
460 RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3),
461
462 /* SOFTRST_CON63 */
463 RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5),
464 RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7),
465 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
466 RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10),
467 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12),
468 RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13),
469 RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14),
470
471 /* SOFTRST_CON64 */
472 RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5),
473 RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6),
474 RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7),
475 RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
476 RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13),
477 RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14),
478
479 /* SOFTRST_CON65 */
480 RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4),
481 RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5),
482 RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8),
483 RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
484 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10),
485 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13),
486 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14),
487 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15),
488
489 /* SOFTRST_CON66 */
490 RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0),
491 RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2),
492
493 /* SOFTRST_CON67 */
494 RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5),
495 RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6),
496 RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
497 RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10),
498 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11),
499 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12),
500 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13),
501 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14),
502
503 /* SOFTRST_CON68 */
504 RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0),
505 RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2),
506 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3),
507 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4),
508 RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5),
509 RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6),
510 RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
511 RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11),
512 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12),
513 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13),
514
515 /* SOFTRST_CON69 */
516 RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3),
517 RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6),
518 RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
519 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
520 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13),
521 RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14),
522 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15),
523
524 /* SOFTRST_CON72 */
525 RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4),
526 RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5),
527 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6),
528 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7),
529 RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8),
530 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
531 RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10),
532 RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11),
533 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12),
534
535 /* SOFTRST_CON75 */
536 RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1),
537
538 /* SOFTRST_CON78 */
539 RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1),
540 RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2),
541 RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3),
542 RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4),
543
544 /* SOFTRST_CON79 */
545 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1),
546 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2),
547 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3),
548 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4),
549 RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5),
550
551 /* PPLL_SOFTRST_CON00 */
552 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1),
553 RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3),
554 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5),
555 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6),
556 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
557 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8),
558
559 /* PPLL_SOFTRST_CON01 */
560 RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5),
561 RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8),
562
563 /* SECURENS_SOFTRST_CON00 */
564 RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3),
565 RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4),
566 RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8),
567 RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
568
569 /* PMU1_SOFTRST_CON00 */
570 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0),
571 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
572 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
573 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
574 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4),
575 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5),
576 RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6),
577 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
578 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
579 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
580 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10),
581 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
582 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12),
583 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
584
585 /* PMU1_SOFTRST_CON01 */
586 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
587 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1),
588 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
589 RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
590 RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4),
591 RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5),
592 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6),
593 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
594 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
595 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
596 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10),
597 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
598 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13),
599
600 /* PMU1_SOFTRST_CON02 */
601 RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
602 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
603 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
604
605 /* PMU1_SOFTRST_CON03 */
606 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
607 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10),
608 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
609 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12),
610 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13),
611
612 /* PMU1_SOFTRST_CON04 */
613 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1),
614 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3),
615 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4),
616 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5),
617 RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6),
618 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
619 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
620 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10),
621 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),
622 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12),
623
624 /* PMU1_SOFTRST_CON05 */
625 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1),
626 RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),
627 RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5),
628 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6),
629 RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13),
630 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15),
631
632 /* PMU1_SOFTRST_CON06 */
633 RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0),
634 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1),
635
636 /* PMU1_SOFTRST_CON07 */
637 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
638 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
639 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
640 RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),
641};
642
643int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
644{
645 return rockchip_reset_bind_lut(pdev, rk3576_register_offset,
646 reg_offset, reg_number);
647}