| Bin Meng | 8a8694d | 2018-09-26 06:55:21 -0700 | [diff] [blame] | 1 | QEMU RISC-V 'VIRT' BOARD |
| 2 | M: Bin Meng <bmeng.cn@gmail.com> |
| 3 | S: Maintained |
| 4 | F: board/emulation/qemu-riscv/ |
| 5 | F: include/configs/qemu-riscv.h |
| 6 | F: configs/qemu-riscv32_defconfig |
| Anup Patel | 1929fe2 | 2018-12-03 10:57:42 +0530 | [diff] [blame] | 7 | F: configs/qemu-riscv32_smode_defconfig |
| Lukas Auer | df3f100 | 2019-08-21 21:14:49 +0200 | [diff] [blame] | 8 | F: configs/qemu-riscv32_spl_defconfig |
| Bin Meng | 8a8694d | 2018-09-26 06:55:21 -0700 | [diff] [blame] | 9 | F: configs/qemu-riscv64_defconfig |
| Anup Patel | 1929fe2 | 2018-12-03 10:57:42 +0530 | [diff] [blame] | 10 | F: configs/qemu-riscv64_smode_defconfig |
| Lukas Auer | df3f100 | 2019-08-21 21:14:49 +0200 | [diff] [blame] | 11 | F: configs/qemu-riscv64_spl_defconfig |