Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Bryan Wu | 97adb22 | 2014-06-24 11:45:29 +0900 | [diff] [blame] | 2 | /* |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 3 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
Bryan Wu | 97adb22 | 2014-06-24 11:45:29 +0900 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* Tegra vpr routines */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/tegra.h> |
| 11 | #include <asm/arch/mc.h> |
Stephen Warren | 8eadc5f | 2018-07-31 12:39:07 -0600 | [diff] [blame] | 12 | #include <asm/arch-tegra/ap.h> |
Bryan Wu | 97adb22 | 2014-06-24 11:45:29 +0900 | [diff] [blame] | 13 | |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 14 | #include <fdt_support.h> |
| 15 | |
| 16 | static bool _configured; |
| 17 | |
Alexandre Courbot | f36729d | 2015-10-19 13:57:03 +0900 | [diff] [blame] | 18 | void tegra_gpu_config(void) |
Bryan Wu | 97adb22 | 2014-06-24 11:45:29 +0900 | [diff] [blame] | 19 | { |
| 20 | struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; |
| 21 | |
Stephen Warren | 8eadc5f | 2018-07-31 12:39:07 -0600 | [diff] [blame] | 22 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) |
| 23 | if (!tegra_cpu_is_non_secure()) |
| 24 | #endif |
| 25 | { |
| 26 | /* Turn VPR off */ |
| 27 | writel(0, &mc->mc_video_protect_size_mb); |
| 28 | writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, |
| 29 | &mc->mc_video_protect_reg_ctrl); |
| 30 | /* read back to ensure the write went through */ |
| 31 | readl(&mc->mc_video_protect_reg_ctrl); |
| 32 | } |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 33 | |
| 34 | debug("configured VPR\n"); |
| 35 | |
| 36 | _configured = true; |
| 37 | } |
| 38 | |
Alexandre Courbot | 5e270dc | 2015-07-09 16:33:01 +0900 | [diff] [blame] | 39 | #if defined(CONFIG_OF_LIBFDT) |
| 40 | |
Stephen Warren | f4949cd | 2016-04-12 11:17:39 -0600 | [diff] [blame] | 41 | int tegra_gpu_enable_node(void *blob, const char *compat) |
Alexandre Courbot | 5e270dc | 2015-07-09 16:33:01 +0900 | [diff] [blame] | 42 | { |
| 43 | int offset; |
| 44 | |
Stephen Warren | f4949cd | 2016-04-12 11:17:39 -0600 | [diff] [blame] | 45 | if (!_configured) |
| 46 | return 0; |
| 47 | |
| 48 | offset = fdt_node_offset_by_compatible(blob, -1, compat); |
| 49 | while (offset != -FDT_ERR_NOTFOUND) { |
| 50 | fdt_status_okay(blob, offset); |
| 51 | offset = fdt_node_offset_by_compatible(blob, offset, compat); |
Alexandre Courbot | 5e270dc | 2015-07-09 16:33:01 +0900 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | #endif |