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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hans de Goededea16d22015-02-04 12:14:56 +01002/*
3 * DRAM init helper functions
4 *
5 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
Hans de Goededea16d22015-02-04 12:14:56 +01006 */
7
Andre Przywara7a2b2612024-01-03 00:12:26 +00008#include <config.h>
Simon Glass495a5dc2019-11-14 12:57:30 -07009#include <time.h>
Andre Przywara7a2b2612024-01-03 00:12:26 +000010#include <vsprintf.h>
Andre Przywarae996bc62016-05-12 12:14:41 +010011#include <asm/barriers.h>
Hans de Goededea16d22015-02-04 12:14:56 +010012#include <asm/io.h>
13#include <asm/arch/dram.h>
14
15/*
16 * Wait up to 1s for value to be set in given part of reg.
17 */
18void mctl_await_completion(u32 *reg, u32 mask, u32 val)
19{
20 unsigned long tmo = timer_get_us() + 1000000;
21
22 while ((readl(reg) & mask) != val) {
23 if (timer_get_us() > tmo)
24 panic("Timeout initialising DRAM\n");
25 }
26}
27
28/*
Andrey Skvortsovf89d68f2023-12-28 00:28:42 +030029 * Test if memory at offset matches memory at a certain base
Icenowy Zheng8701e102022-01-29 10:23:04 -050030 *
31 * Note: dsb() is not available on ARMv5 in Thumb mode
Hans de Goededea16d22015-02-04 12:14:56 +010032 */
Icenowy Zheng8701e102022-01-29 10:23:04 -050033#ifndef CONFIG_MACH_SUNIV
Andrey Skvortsovf89d68f2023-12-28 00:28:42 +030034bool mctl_mem_matches_base(u32 offset, ulong base)
Hans de Goededea16d22015-02-04 12:14:56 +010035{
36 /* Try to write different values to RAM at two addresses */
Andrey Skvortsovf89d68f2023-12-28 00:28:42 +030037 writel(0, base);
38 writel(0xaa55aa55, base + offset);
Tom Rini3b787ef2016-08-01 18:54:53 -040039 dsb();
Hans de Goededea16d22015-02-04 12:14:56 +010040 /* Check if the same value is actually observed when reading back */
Andrey Skvortsovf89d68f2023-12-28 00:28:42 +030041 return readl(base) ==
42 readl(base + offset);
43}
44
45/*
46 * Test if memory at offset matches memory at begin of DRAM
47 */
48bool mctl_mem_matches(u32 offset)
49{
50 return mctl_mem_matches_base(offset, CFG_SYS_SDRAM_BASE);
Hans de Goededea16d22015-02-04 12:14:56 +010051}
Icenowy Zheng8701e102022-01-29 10:23:04 -050052#endif