Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Hans de Goede | dea16d2 | 2015-02-04 12:14:56 +0100 | [diff] [blame] | 2 | /* |
| 3 | * DRAM init helper functions |
| 4 | * |
| 5 | * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> |
Hans de Goede | dea16d2 | 2015-02-04 12:14:56 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
Andre Przywara | 7a2b261 | 2024-01-03 00:12:26 +0000 | [diff] [blame] | 8 | #include <config.h> |
Simon Glass | 495a5dc | 2019-11-14 12:57:30 -0700 | [diff] [blame] | 9 | #include <time.h> |
Andre Przywara | 7a2b261 | 2024-01-03 00:12:26 +0000 | [diff] [blame] | 10 | #include <vsprintf.h> |
Andre Przywara | e996bc6 | 2016-05-12 12:14:41 +0100 | [diff] [blame] | 11 | #include <asm/barriers.h> |
Hans de Goede | dea16d2 | 2015-02-04 12:14:56 +0100 | [diff] [blame] | 12 | #include <asm/io.h> |
| 13 | #include <asm/arch/dram.h> |
| 14 | |
| 15 | /* |
| 16 | * Wait up to 1s for value to be set in given part of reg. |
| 17 | */ |
| 18 | void mctl_await_completion(u32 *reg, u32 mask, u32 val) |
| 19 | { |
| 20 | unsigned long tmo = timer_get_us() + 1000000; |
| 21 | |
| 22 | while ((readl(reg) & mask) != val) { |
| 23 | if (timer_get_us() > tmo) |
| 24 | panic("Timeout initialising DRAM\n"); |
| 25 | } |
| 26 | } |
| 27 | |
| 28 | /* |
Andrey Skvortsov | f89d68f | 2023-12-28 00:28:42 +0300 | [diff] [blame^] | 29 | * Test if memory at offset matches memory at a certain base |
Icenowy Zheng | 8701e10 | 2022-01-29 10:23:04 -0500 | [diff] [blame] | 30 | * |
| 31 | * Note: dsb() is not available on ARMv5 in Thumb mode |
Hans de Goede | dea16d2 | 2015-02-04 12:14:56 +0100 | [diff] [blame] | 32 | */ |
Icenowy Zheng | 8701e10 | 2022-01-29 10:23:04 -0500 | [diff] [blame] | 33 | #ifndef CONFIG_MACH_SUNIV |
Andrey Skvortsov | f89d68f | 2023-12-28 00:28:42 +0300 | [diff] [blame^] | 34 | bool mctl_mem_matches_base(u32 offset, ulong base) |
Hans de Goede | dea16d2 | 2015-02-04 12:14:56 +0100 | [diff] [blame] | 35 | { |
| 36 | /* Try to write different values to RAM at two addresses */ |
Andrey Skvortsov | f89d68f | 2023-12-28 00:28:42 +0300 | [diff] [blame^] | 37 | writel(0, base); |
| 38 | writel(0xaa55aa55, base + offset); |
Tom Rini | 3b787ef | 2016-08-01 18:54:53 -0400 | [diff] [blame] | 39 | dsb(); |
Hans de Goede | dea16d2 | 2015-02-04 12:14:56 +0100 | [diff] [blame] | 40 | /* Check if the same value is actually observed when reading back */ |
Andrey Skvortsov | f89d68f | 2023-12-28 00:28:42 +0300 | [diff] [blame^] | 41 | return readl(base) == |
| 42 | readl(base + offset); |
| 43 | } |
| 44 | |
| 45 | /* |
| 46 | * Test if memory at offset matches memory at begin of DRAM |
| 47 | */ |
| 48 | bool mctl_mem_matches(u32 offset) |
| 49 | { |
| 50 | return mctl_mem_matches_base(offset, CFG_SYS_SDRAM_BASE); |
Hans de Goede | dea16d2 | 2015-02-04 12:14:56 +0100 | [diff] [blame] | 51 | } |
Icenowy Zheng | 8701e10 | 2022-01-29 10:23:04 -0500 | [diff] [blame] | 52 | #endif |