blob: 16169dac23409fc8b49289be22f5783a7024a791 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass36ad2342015-06-23 15:39:15 -06002/*
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Stephen Warrena9622432016-06-17 09:44:00 -06005 * Copyright (c) 2016, NVIDIA CORPORATION.
Philipp Tomsich9cf03b02018-01-08 13:59:18 +01006 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
Simon Glass36ad2342015-06-23 15:39:15 -06007 */
8
Patrick Delaunay81313352021-04-27 11:02:19 +02009#define LOG_CATEGORY UCLASS_CLK
10
Simon Glass36ad2342015-06-23 15:39:15 -060011#include <clk.h>
Stephen Warrena9622432016-06-17 09:44:00 -060012#include <clk-uclass.h>
Simon Glass36ad2342015-06-23 15:39:15 -060013#include <dm.h>
Simon Glass589d9152016-07-04 11:58:03 -060014#include <dt-structs.h>
Simon Glass36ad2342015-06-23 15:39:15 -060015#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070017#include <malloc.h>
Patrick Delaunay283dadf2021-11-19 15:12:06 +010018#include <asm/global_data.h>
Sean Andersond7ac3732021-04-08 22:13:03 -040019#include <dm/device_compat.h>
Claudiu Bezneac8c16002020-09-07 17:46:34 +030020#include <dm/device-internal.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070021#include <dm/devres.h>
22#include <dm/read.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060023#include <linux/bug.h>
Lukasz Majewski9e38dc32019-06-24 15:50:42 +020024#include <linux/clk-provider.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070025#include <linux/err.h>
Simon Glass36ad2342015-06-23 15:39:15 -060026
Mario Six799fe562018-01-15 11:06:51 +010027static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
Simon Glass36ad2342015-06-23 15:39:15 -060028{
Mario Six799fe562018-01-15 11:06:51 +010029 return (const struct clk_ops *)dev->driver->ops;
Simon Glass36ad2342015-06-23 15:39:15 -060030}
31
Simon Glass43033962020-07-19 10:15:56 -060032struct clk *dev_get_clk_ptr(struct udevice *dev)
33{
34 return (struct clk *)dev_get_uclass_priv(dev);
35}
36
Simon Glass3580f6d2021-08-07 07:24:03 -060037#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass1257efc2021-08-07 07:24:09 -060038int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells,
39 struct clk *clk)
Simon Glass589d9152016-07-04 11:58:03 -060040{
41 int ret;
42
Simon Glass0000e0d2021-03-15 17:25:28 +130043 ret = device_get_by_ofplat_idx(cells->idx, &clk->dev);
Simon Glass589d9152016-07-04 11:58:03 -060044 if (ret)
45 return ret;
Walter Lozanodc5b4372020-06-25 01:10:13 -030046 clk->id = cells->arg[0];
Simon Glass589d9152016-07-04 11:58:03 -060047
48 return 0;
49}
Simon Glass3580f6d2021-08-07 07:24:03 -060050#endif
51
52#if CONFIG_IS_ENABLED(OF_REAL)
Stephen Warrena9622432016-06-17 09:44:00 -060053static int clk_of_xlate_default(struct clk *clk,
Simon Glassb7ae2772017-05-18 20:09:40 -060054 struct ofnode_phandle_args *args)
Simon Glass36ad2342015-06-23 15:39:15 -060055{
Stephen Warrena9622432016-06-17 09:44:00 -060056 debug("%s(clk=%p)\n", __func__, clk);
Simon Glass36ad2342015-06-23 15:39:15 -060057
Stephen Warrena9622432016-06-17 09:44:00 -060058 if (args->args_count > 1) {
Sean Andersona1b654b2021-12-01 14:26:53 -050059 debug("Invalid args_count: %d\n", args->args_count);
Stephen Warrena9622432016-06-17 09:44:00 -060060 return -EINVAL;
61 }
Simon Glass36ad2342015-06-23 15:39:15 -060062
Stephen Warrena9622432016-06-17 09:44:00 -060063 if (args->args_count)
64 clk->id = args->args[0];
65 else
66 clk->id = 0;
Simon Glass36ad2342015-06-23 15:39:15 -060067
Sekhar Nori3d23abd2019-07-11 14:30:24 +053068 clk->data = 0;
69
Stephen Warrena9622432016-06-17 09:44:00 -060070 return 0;
Simon Glass36ad2342015-06-23 15:39:15 -060071}
Simon Glass0342bd22016-01-20 19:43:02 -070072
Jagan Tekifc7c7ce2019-02-28 00:26:52 +053073static int clk_get_by_index_tail(int ret, ofnode node,
74 struct ofnode_phandle_args *args,
75 const char *list_name, int index,
76 struct clk *clk)
77{
78 struct udevice *dev_clk;
79 const struct clk_ops *ops;
80
81 assert(clk);
82 clk->dev = NULL;
83 if (ret)
84 goto err;
85
86 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
87 if (ret) {
88 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
89 __func__, ret);
Simon Glassf73f5812021-01-21 13:57:11 -070090 return log_msg_ret("get", ret);
Jagan Tekifc7c7ce2019-02-28 00:26:52 +053091 }
92
93 clk->dev = dev_clk;
94
95 ops = clk_dev_ops(dev_clk);
96
97 if (ops->of_xlate)
98 ret = ops->of_xlate(clk, args);
99 else
100 ret = clk_of_xlate_default(clk, args);
101 if (ret) {
102 debug("of_xlate() failed: %d\n", ret);
Simon Glassf73f5812021-01-21 13:57:11 -0700103 return log_msg_ret("xlate", ret);
Jagan Tekifc7c7ce2019-02-28 00:26:52 +0530104 }
105
106 return clk_request(dev_clk, clk);
107err:
108 debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
109 __func__, ofnode_get_name(node), list_name, index, ret);
Simon Glassf73f5812021-01-21 13:57:11 -0700110
111 return log_msg_ret("prop", ret);
Jagan Tekifc7c7ce2019-02-28 00:26:52 +0530112}
113
Philipp Tomsichf7604342018-01-08 11:18:18 +0100114static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
115 int index, struct clk *clk)
Simon Glass0342bd22016-01-20 19:43:02 -0700116{
Simon Glass0342bd22016-01-20 19:43:02 -0700117 int ret;
Simon Glass2558bff2017-05-30 21:47:29 -0600118 struct ofnode_phandle_args args;
Simon Glass0342bd22016-01-20 19:43:02 -0700119
Stephen Warrena9622432016-06-17 09:44:00 -0600120 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
121
122 assert(clk);
Patrice Chotard96fc03d2017-07-18 11:57:07 +0200123 clk->dev = NULL;
124
Philipp Tomsichf7604342018-01-08 11:18:18 +0100125 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
Mario Six799fe562018-01-15 11:06:51 +0100126 index, &args);
Simon Glass0342bd22016-01-20 19:43:02 -0700127 if (ret) {
128 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
129 __func__, ret);
Simon Glassf73f5812021-01-21 13:57:11 -0700130 return log_ret(ret);
Simon Glass0342bd22016-01-20 19:43:02 -0700131 }
132
Jagan Tekia77add32019-02-28 00:26:53 +0530133 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
Sean Andersonf0d5a6b2020-06-24 06:41:08 -0400134 index, clk);
Stephen Warrena9622432016-06-17 09:44:00 -0600135}
Philipp Tomsichf7604342018-01-08 11:18:18 +0100136
137int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
138{
Sean Anderson07435de2022-02-27 14:01:13 -0500139 return clk_get_by_index_nodev(dev_ofnode(dev), index, clk);
Jagan Tekifc7c7ce2019-02-28 00:26:52 +0530140}
141
142int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
143{
144 struct ofnode_phandle_args args;
145 int ret;
146
147 ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
Sean Andersonf0d5a6b2020-06-24 06:41:08 -0400148 index, &args);
Jagan Tekifc7c7ce2019-02-28 00:26:52 +0530149
150 return clk_get_by_index_tail(ret, node, &args, "clocks",
Sean Andersonf0d5a6b2020-06-24 06:41:08 -0400151 index, clk);
Philipp Tomsichf7604342018-01-08 11:18:18 +0100152}
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100153
Neil Armstrong8a275a02018-04-03 11:44:18 +0200154int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
155{
156 int i, ret, err, count;
Patrick Delaunayb9c32142021-04-27 10:57:54 +0200157
Neil Armstrong8a275a02018-04-03 11:44:18 +0200158 bulk->count = 0;
159
Patrick Delaunayd776a842020-09-25 09:41:14 +0200160 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 0);
Neil Armstrong52b26d92018-04-17 11:30:31 +0200161 if (count < 1)
162 return count;
Neil Armstrong8a275a02018-04-03 11:44:18 +0200163
164 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
165 if (!bulk->clks)
166 return -ENOMEM;
167
168 for (i = 0; i < count; i++) {
169 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
170 if (ret < 0)
171 goto bulk_get_err;
172
173 ++bulk->count;
174 }
175
176 return 0;
177
178bulk_get_err:
179 err = clk_release_all(bulk->clks, bulk->count);
180 if (err)
Jan Kiszka46bba6e2024-03-09 13:27:09 +0100181 debug("%s: could not release all clocks for %p\n",
Neil Armstrong8a275a02018-04-03 11:44:18 +0200182 __func__, dev);
183
184 return ret;
185}
186
Claudiu Bezneab91eee62020-09-07 17:46:36 +0300187static struct clk *clk_set_default_get_by_id(struct clk *clk)
188{
189 struct clk *c = clk;
190
191 if (CONFIG_IS_ENABLED(CLK_CCF)) {
192 int ret = clk_get_by_id(clk->id, &c);
193
194 if (ret) {
195 debug("%s(): could not get parent clock pointer, id %lu\n",
196 __func__, clk->id);
197 ERR_PTR(ret);
198 }
199 }
200
201 return c;
202}
203
Sean Anderson08d531c2021-06-11 00:16:07 -0400204static int clk_set_default_parents(struct udevice *dev,
205 enum clk_defaults_stage stage)
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100206{
Claudiu Bezneab91eee62020-09-07 17:46:36 +0300207 struct clk clk, parent_clk, *c, *p;
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100208 int index;
209 int num_parents;
210 int ret;
211
212 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
Patrick Delaunayd776a842020-09-25 09:41:14 +0200213 "#clock-cells", 0);
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100214 if (num_parents < 0) {
215 debug("%s: could not read assigned-clock-parents for %p\n",
216 __func__, dev);
217 return 0;
218 }
219
220 for (index = 0; index < num_parents; index++) {
221 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
222 index, &parent_clk);
Neil Armstrongf3cc6312018-07-26 15:19:32 +0200223 /* If -ENOENT, this is a no-op entry */
224 if (ret == -ENOENT)
225 continue;
226
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100227 if (ret) {
228 debug("%s: could not get parent clock %d for %s\n",
229 __func__, index, dev_read_name(dev));
230 return ret;
231 }
232
Claudiu Bezneab91eee62020-09-07 17:46:36 +0300233 p = clk_set_default_get_by_id(&parent_clk);
234 if (IS_ERR(p))
235 return PTR_ERR(p);
236
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100237 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
238 index, &clk);
Tero Kristod41b2b32021-06-11 11:45:11 +0300239 /*
240 * If the clock provider is not ready yet, let it handle
241 * the re-programming later.
242 */
243 if (ret == -EPROBE_DEFER) {
244 ret = 0;
245 continue;
246 }
247
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100248 if (ret) {
249 debug("%s: could not get assigned clock %d for %s\n",
250 __func__, index, dev_read_name(dev));
251 return ret;
252 }
253
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200254 /* This is clk provider device trying to reparent itself
255 * It cannot be done right now but need to wait after the
256 * device is probed
257 */
Sean Anderson08d531c2021-06-11 00:16:07 -0400258 if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200259 continue;
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100260
Sean Anderson08d531c2021-06-11 00:16:07 -0400261 if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200262 /* do not setup twice the parent clocks */
263 continue;
264
Claudiu Bezneab91eee62020-09-07 17:46:36 +0300265 c = clk_set_default_get_by_id(&clk);
266 if (IS_ERR(c))
267 return PTR_ERR(c);
268
269 ret = clk_set_parent(c, p);
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100270 /*
271 * Not all drivers may support clock-reparenting (as of now).
272 * Ignore errors due to this.
273 */
274 if (ret == -ENOSYS)
275 continue;
276
Jean-Jacques Hiblotb2320812019-09-26 15:42:42 +0200277 if (ret < 0) {
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100278 debug("%s: failed to reparent clock %d for %s\n",
279 __func__, index, dev_read_name(dev));
280 return ret;
281 }
282 }
283
284 return 0;
285}
286
Sean Anderson08d531c2021-06-11 00:16:07 -0400287static int clk_set_default_rates(struct udevice *dev,
288 enum clk_defaults_stage stage)
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100289{
Claudiu Bezneab91eee62020-09-07 17:46:36 +0300290 struct clk clk, *c;
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100291 int index;
292 int num_rates;
293 int size;
294 int ret = 0;
295 u32 *rates = NULL;
296
297 size = dev_read_size(dev, "assigned-clock-rates");
298 if (size < 0)
299 return 0;
300
301 num_rates = size / sizeof(u32);
302 rates = calloc(num_rates, sizeof(u32));
303 if (!rates)
304 return -ENOMEM;
305
306 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
307 if (ret)
308 goto fail;
309
310 for (index = 0; index < num_rates; index++) {
Neil Armstrongf3cc6312018-07-26 15:19:32 +0200311 /* If 0 is passed, this is a no-op */
312 if (!rates[index])
313 continue;
314
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100315 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
316 index, &clk);
Tero Kristod41b2b32021-06-11 11:45:11 +0300317 /*
318 * If the clock provider is not ready yet, let it handle
319 * the re-programming later.
320 */
321 if (ret == -EPROBE_DEFER) {
322 ret = 0;
323 continue;
324 }
325
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100326 if (ret) {
Sean Andersond7ac3732021-04-08 22:13:03 -0400327 dev_dbg(dev,
328 "could not get assigned clock %d (err = %d)\n",
329 index, ret);
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200330 /* Skip if it is empty */
331 if (ret == -ENOENT) {
332 ret = 0;
333 continue;
334 }
335
336 return ret;
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100337 }
338
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200339 /* This is clk provider device trying to program itself
340 * It cannot be done right now but need to wait after the
341 * device is probed
342 */
Sean Anderson08d531c2021-06-11 00:16:07 -0400343 if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200344 continue;
345
Sean Anderson08d531c2021-06-11 00:16:07 -0400346 if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200347 /* do not setup twice the parent clocks */
348 continue;
349
Claudiu Bezneab91eee62020-09-07 17:46:36 +0300350 c = clk_set_default_get_by_id(&clk);
351 if (IS_ERR(c))
352 return PTR_ERR(c);
353
354 ret = clk_set_rate(c, rates[index]);
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200355
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100356 if (ret < 0) {
Sean Andersond7ac3732021-04-08 22:13:03 -0400357 dev_warn(dev,
358 "failed to set rate on clock index %d (%ld) (error = %d)\n",
359 index, clk.id, ret);
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100360 break;
361 }
362 }
363
364fail:
365 free(rates);
366 return ret;
367}
368
Sean Anderson08d531c2021-06-11 00:16:07 -0400369int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage)
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100370{
371 int ret;
372
Simon Glassf1d50f72020-12-19 10:40:13 -0700373 if (!dev_has_ofnode(dev))
Peng Fan40ec4e42019-07-31 07:01:49 +0000374 return 0;
375
Sean Anderson08d531c2021-06-11 00:16:07 -0400376 /*
377 * To avoid setting defaults twice, don't set them before relocation.
378 * However, still set them for SPL. And still set them if explicitly
379 * asked.
380 */
Philipp Tomsiche546ec82018-11-26 20:20:19 +0100381 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
Sean Anderson08d531c2021-06-11 00:16:07 -0400382 if (stage != CLK_DEFAULTS_POST_FORCE)
383 return 0;
Philipp Tomsiche546ec82018-11-26 20:20:19 +0100384
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100385 debug("%s(%s)\n", __func__, dev_read_name(dev));
386
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200387 ret = clk_set_default_parents(dev, stage);
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100388 if (ret)
389 return ret;
390
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200391 ret = clk_set_default_rates(dev, stage);
Philipp Tomsich9cf03b02018-01-08 13:59:18 +0100392 if (ret < 0)
393 return ret;
394
395 return 0;
396}
Stephen Warrena9622432016-06-17 09:44:00 -0600397
398int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
399{
Sean Anderson07435de2022-02-27 14:01:13 -0500400 return clk_get_by_name_nodev(dev_ofnode(dev), name, clk);
Simon Glass0342bd22016-01-20 19:43:02 -0700401}
Simon Glass1257efc2021-08-07 07:24:09 -0600402#endif /* OF_REAL */
Patrice Chotardcafc3412017-07-25 13:24:45 +0200403
developerbdc786d2020-01-09 11:35:07 +0800404int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
405{
Samuel Hollandbae0f4f2023-01-21 18:02:51 -0600406 int index = 0;
developerbdc786d2020-01-09 11:35:07 +0800407
408 debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
409 ofnode_get_name(node), name, clk);
410 clk->dev = NULL;
411
Samuel Hollandbae0f4f2023-01-21 18:02:51 -0600412 if (name) {
413 index = ofnode_stringlist_search(node, "clock-names", name);
414 if (index < 0) {
415 debug("fdt_stringlist_search() failed: %d\n", index);
416 return index;
417 }
developerbdc786d2020-01-09 11:35:07 +0800418 }
419
420 return clk_get_by_index_nodev(node, index, clk);
421}
422
Eugen Hristev70e32ba2023-06-19 13:47:52 +0300423int clk_release_all(struct clk *clk, unsigned int count)
Patrice Chotardcafc3412017-07-25 13:24:45 +0200424{
Eugen Hristev70e32ba2023-06-19 13:47:52 +0300425 unsigned int i;
426 int ret;
Patrice Chotardcafc3412017-07-25 13:24:45 +0200427
428 for (i = 0; i < count; i++) {
Eugen Hristev70e32ba2023-06-19 13:47:52 +0300429 debug("%s(clk[%u]=%p)\n", __func__, i, &clk[i]);
Patrice Chotardcafc3412017-07-25 13:24:45 +0200430
431 /* check if clock has been previously requested */
432 if (!clk[i].dev)
433 continue;
434
435 ret = clk_disable(&clk[i]);
436 if (ret && ret != -ENOSYS)
437 return ret;
Patrice Chotardcafc3412017-07-25 13:24:45 +0200438 }
439
440 return 0;
441}
442
Stephen Warrena9622432016-06-17 09:44:00 -0600443int clk_request(struct udevice *dev, struct clk *clk)
444{
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200445 const struct clk_ops *ops;
Stephen Warrena9622432016-06-17 09:44:00 -0600446
447 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200448 if (!clk)
449 return 0;
450 ops = clk_dev_ops(dev);
Stephen Warrena9622432016-06-17 09:44:00 -0600451
452 clk->dev = dev;
453
454 if (!ops->request)
455 return 0;
456
457 return ops->request(clk);
458}
459
Stephen Warrena9622432016-06-17 09:44:00 -0600460ulong clk_get_rate(struct clk *clk)
461{
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200462 const struct clk_ops *ops;
Stephen Warrena9622432016-06-17 09:44:00 -0600463
464 debug("%s(clk=%p)\n", __func__, clk);
developerdc338d32020-01-09 11:35:06 +0800465 if (!clk_valid(clk))
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200466 return 0;
467 ops = clk_dev_ops(clk->dev);
Stephen Warrena9622432016-06-17 09:44:00 -0600468
469 if (!ops->get_rate)
470 return -ENOSYS;
471
Julien Massonb5de0b92023-12-15 15:09:43 +0100472 return ops->get_rate(clk);
Stephen Warrena9622432016-06-17 09:44:00 -0600473}
474
Lukasz Majewski9e38dc32019-06-24 15:50:42 +0200475struct clk *clk_get_parent(struct clk *clk)
476{
477 struct udevice *pdev;
478 struct clk *pclk;
479
480 debug("%s(clk=%p)\n", __func__, clk);
developerdc338d32020-01-09 11:35:06 +0800481 if (!clk_valid(clk))
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200482 return NULL;
Lukasz Majewski9e38dc32019-06-24 15:50:42 +0200483
484 pdev = dev_get_parent(clk->dev);
Tero Kristof04dfff2021-06-11 11:45:08 +0300485 if (!pdev)
486 return ERR_PTR(-ENODEV);
Lukasz Majewski9e38dc32019-06-24 15:50:42 +0200487 pclk = dev_get_clk_ptr(pdev);
488 if (!pclk)
489 return ERR_PTR(-ENODEV);
490
491 return pclk;
492}
493
Michal Suchanek0d4d5e42022-09-28 12:37:57 +0200494ulong clk_get_parent_rate(struct clk *clk)
Lukasz Majewski53155da2019-06-24 15:50:43 +0200495{
496 const struct clk_ops *ops;
497 struct clk *pclk;
498
499 debug("%s(clk=%p)\n", __func__, clk);
developerdc338d32020-01-09 11:35:06 +0800500 if (!clk_valid(clk))
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200501 return 0;
Lukasz Majewski53155da2019-06-24 15:50:43 +0200502
503 pclk = clk_get_parent(clk);
504 if (IS_ERR(pclk))
505 return -ENODEV;
506
507 ops = clk_dev_ops(pclk->dev);
508 if (!ops->get_rate)
509 return -ENOSYS;
510
Lukasz Majewski4ef32172019-06-24 15:50:46 +0200511 /* Read the 'rate' if not already set or if proper flag set*/
512 if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
Lukasz Majewski53155da2019-06-24 15:50:43 +0200513 pclk->rate = clk_get_rate(pclk);
514
515 return pclk->rate;
516}
517
Dario Binacchib7f85892020-12-30 00:06:31 +0100518ulong clk_round_rate(struct clk *clk, ulong rate)
519{
520 const struct clk_ops *ops;
521
522 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
523 if (!clk_valid(clk))
524 return 0;
525
526 ops = clk_dev_ops(clk->dev);
527 if (!ops->round_rate)
528 return -ENOSYS;
529
530 return ops->round_rate(clk, rate);
531}
532
Patrick Delaunayd867a2872022-06-20 15:37:25 +0200533static void clk_get_priv(struct clk *clk, struct clk **clkp)
534{
535 *clkp = clk;
536
537 /* get private clock struct associated to the provided clock */
538 if (CONFIG_IS_ENABLED(CLK_CCF)) {
539 /* Take id 0 as a non-valid clk, such as dummy */
540 if (clk->id)
541 clk_get_by_id(clk->id, clkp);
542 }
543}
544
545/* clean cache, called with private clock struct */
Tero Kristo9ab78c12021-06-11 11:45:12 +0300546static void clk_clean_rate_cache(struct clk *clk)
547{
548 struct udevice *child_dev;
549 struct clk *clkp;
550
551 if (!clk)
552 return;
553
554 clk->rate = 0;
555
556 list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
557 clkp = dev_get_clk_ptr(child_dev);
558 clk_clean_rate_cache(clkp);
559 }
560}
561
Stephen Warrena9622432016-06-17 09:44:00 -0600562ulong clk_set_rate(struct clk *clk, ulong rate)
563{
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200564 const struct clk_ops *ops;
Patrick Delaunayd867a2872022-06-20 15:37:25 +0200565 struct clk *clkp;
Stephen Warrena9622432016-06-17 09:44:00 -0600566
567 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
developerdc338d32020-01-09 11:35:06 +0800568 if (!clk_valid(clk))
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200569 return 0;
570 ops = clk_dev_ops(clk->dev);
Stephen Warrena9622432016-06-17 09:44:00 -0600571
572 if (!ops->set_rate)
573 return -ENOSYS;
574
Patrick Delaunayd867a2872022-06-20 15:37:25 +0200575 /* get private clock struct used for cache */
576 clk_get_priv(clk, &clkp);
Tero Kristo9ab78c12021-06-11 11:45:12 +0300577 /* Clean up cached rates for us and all child clocks */
Patrick Delaunayd867a2872022-06-20 15:37:25 +0200578 clk_clean_rate_cache(clkp);
Tero Kristo9ab78c12021-06-11 11:45:12 +0300579
Stephen Warrena9622432016-06-17 09:44:00 -0600580 return ops->set_rate(clk, rate);
581}
582
Philipp Tomsichf8e02b22018-01-08 11:15:08 +0100583int clk_set_parent(struct clk *clk, struct clk *parent)
584{
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200585 const struct clk_ops *ops;
Claudiu Bezneac8c16002020-09-07 17:46:34 +0300586 int ret;
Philipp Tomsichf8e02b22018-01-08 11:15:08 +0100587
588 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
developerdc338d32020-01-09 11:35:06 +0800589 if (!clk_valid(clk))
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200590 return 0;
591 ops = clk_dev_ops(clk->dev);
Philipp Tomsichf8e02b22018-01-08 11:15:08 +0100592
593 if (!ops->set_parent)
594 return -ENOSYS;
595
Claudiu Bezneac8c16002020-09-07 17:46:34 +0300596 ret = ops->set_parent(clk, parent);
597 if (ret)
598 return ret;
599
600 if (CONFIG_IS_ENABLED(CLK_CCF))
601 ret = device_reparent(clk->dev, parent->dev);
602
603 return ret;
Philipp Tomsichf8e02b22018-01-08 11:15:08 +0100604}
605
Stephen Warrena9622432016-06-17 09:44:00 -0600606int clk_enable(struct clk *clk)
607{
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200608 const struct clk_ops *ops;
Peng Fan82628e22019-08-21 13:35:09 +0000609 struct clk *clkp = NULL;
610 int ret;
Stephen Warrena9622432016-06-17 09:44:00 -0600611
Michael Trimarchif84d65c2024-07-09 08:28:13 +0200612 debug("%s(clk=%p name=%s)\n", __func__, clk, clk->dev->name);
developerdc338d32020-01-09 11:35:06 +0800613 if (!clk_valid(clk))
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200614 return 0;
615 ops = clk_dev_ops(clk->dev);
Stephen Warrena9622432016-06-17 09:44:00 -0600616
Peng Fan82628e22019-08-21 13:35:09 +0000617 if (CONFIG_IS_ENABLED(CLK_CCF)) {
618 /* Take id 0 as a non-valid clk, such as dummy */
619 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
Yang Xiwencb34b1c2023-11-19 06:10:06 +0800620 ops = clk_dev_ops(clkp->dev);
Peng Fan82628e22019-08-21 13:35:09 +0000621 if (clkp->enable_count) {
622 clkp->enable_count++;
623 return 0;
624 }
625 if (clkp->dev->parent &&
Patrick Delaunaydb9b1a12022-01-24 14:17:14 +0100626 device_get_uclass_id(clkp->dev->parent) == UCLASS_CLK) {
Peng Fan82628e22019-08-21 13:35:09 +0000627 ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
628 if (ret) {
629 printf("Enable %s failed\n",
630 clkp->dev->parent->name);
631 return ret;
632 }
633 }
634 }
Stephen Warrena9622432016-06-17 09:44:00 -0600635
Peng Fan82628e22019-08-21 13:35:09 +0000636 if (ops->enable) {
Maksim Kiselev77e11512023-09-06 01:16:49 +0300637 ret = ops->enable(clkp ? clkp : clk);
Peng Fan82628e22019-08-21 13:35:09 +0000638 if (ret) {
639 printf("Enable %s failed\n", clk->dev->name);
640 return ret;
641 }
642 }
643 if (clkp)
644 clkp->enable_count++;
645 } else {
646 if (!ops->enable)
647 return -ENOSYS;
648 return ops->enable(clk);
649 }
650
651 return 0;
Stephen Warrena9622432016-06-17 09:44:00 -0600652}
653
Neil Armstrong8a275a02018-04-03 11:44:18 +0200654int clk_enable_bulk(struct clk_bulk *bulk)
655{
656 int i, ret;
657
658 for (i = 0; i < bulk->count; i++) {
659 ret = clk_enable(&bulk->clks[i]);
660 if (ret < 0 && ret != -ENOSYS)
661 return ret;
662 }
663
664 return 0;
665}
666
Stephen Warrena9622432016-06-17 09:44:00 -0600667int clk_disable(struct clk *clk)
668{
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200669 const struct clk_ops *ops;
Peng Fan82628e22019-08-21 13:35:09 +0000670 struct clk *clkp = NULL;
671 int ret;
Stephen Warrena9622432016-06-17 09:44:00 -0600672
Michael Trimarchif84d65c2024-07-09 08:28:13 +0200673 debug("%s(clk=%p name=%s)\n", __func__, clk, clk->dev->name);
developerdc338d32020-01-09 11:35:06 +0800674 if (!clk_valid(clk))
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200675 return 0;
676 ops = clk_dev_ops(clk->dev);
Stephen Warrena9622432016-06-17 09:44:00 -0600677
Peng Fan82628e22019-08-21 13:35:09 +0000678 if (CONFIG_IS_ENABLED(CLK_CCF)) {
679 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
Yang Xiwencb34b1c2023-11-19 06:10:06 +0800680 ops = clk_dev_ops(clkp->dev);
Claudiu Bezneab02e8dd2020-09-07 17:46:35 +0300681 if (clkp->flags & CLK_IS_CRITICAL)
682 return 0;
683
Peng Fan82628e22019-08-21 13:35:09 +0000684 if (clkp->enable_count == 0) {
685 printf("clk %s already disabled\n",
686 clkp->dev->name);
687 return 0;
688 }
Stephen Warrena9622432016-06-17 09:44:00 -0600689
Peng Fan82628e22019-08-21 13:35:09 +0000690 if (--clkp->enable_count > 0)
691 return 0;
692 }
693
694 if (ops->disable) {
Maksim Kiselev77e11512023-09-06 01:16:49 +0300695 ret = ops->disable(clkp ? clkp : clk);
Peng Fan82628e22019-08-21 13:35:09 +0000696 if (ret)
697 return ret;
698 }
699
700 if (clkp && clkp->dev->parent &&
Patrick Delaunaydb9b1a12022-01-24 14:17:14 +0100701 device_get_uclass_id(clkp->dev->parent) == UCLASS_CLK) {
Peng Fan82628e22019-08-21 13:35:09 +0000702 ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
703 if (ret) {
704 printf("Disable %s failed\n",
705 clkp->dev->parent->name);
706 return ret;
707 }
708 }
709 } else {
710 if (!ops->disable)
711 return -ENOSYS;
712
713 return ops->disable(clk);
714 }
715
716 return 0;
Stephen Warrena9622432016-06-17 09:44:00 -0600717}
Simon Glass36ad2342015-06-23 15:39:15 -0600718
Neil Armstrong8a275a02018-04-03 11:44:18 +0200719int clk_disable_bulk(struct clk_bulk *bulk)
720{
721 int i, ret;
722
723 for (i = 0; i < bulk->count; i++) {
724 ret = clk_disable(&bulk->clks[i]);
725 if (ret < 0 && ret != -ENOSYS)
726 return ret;
727 }
728
729 return 0;
730}
731
Lukasz Majewski12014be2019-06-24 15:50:44 +0200732int clk_get_by_id(ulong id, struct clk **clkp)
733{
734 struct udevice *dev;
735 struct uclass *uc;
736 int ret;
737
738 ret = uclass_get(UCLASS_CLK, &uc);
739 if (ret)
740 return ret;
741
742 uclass_foreach_dev(dev, uc) {
743 struct clk *clk = dev_get_clk_ptr(dev);
744
745 if (clk && clk->id == id) {
746 *clkp = clk;
747 return 0;
748 }
749 }
750
751 return -ENOENT;
752}
753
Sekhar Noricf3119d2019-08-01 19:12:55 +0530754bool clk_is_match(const struct clk *p, const struct clk *q)
755{
756 /* trivial case: identical struct clk's or both NULL */
757 if (p == q)
758 return true;
759
Jean-Jacques Hiblot718039b2019-10-22 14:00:03 +0200760 /* trivial case #2: on the clk pointer is NULL */
761 if (!p || !q)
762 return false;
763
Sekhar Noricf3119d2019-08-01 19:12:55 +0530764 /* same device, id and data */
765 if (p->dev == q->dev && p->id == q->id && p->data == q->data)
766 return true;
767
768 return false;
769}
770
Jean-Jacques Hiblot6e66b2d2019-10-22 14:00:04 +0200771struct clk *devm_clk_get(struct udevice *dev, const char *id)
772{
773 int rc;
774 struct clk *clk;
775
Sean Andersond318eb32023-12-16 14:38:42 -0500776 clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
Jean-Jacques Hiblot6e66b2d2019-10-22 14:00:04 +0200777 if (unlikely(!clk))
778 return ERR_PTR(-ENOMEM);
779
780 rc = clk_get_by_name(dev, id, clk);
781 if (rc)
782 return ERR_PTR(rc);
783
Jean-Jacques Hiblot6e66b2d2019-10-22 14:00:04 +0200784 return clk;
785}
786
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200787int clk_uclass_post_probe(struct udevice *dev)
788{
789 /*
790 * when a clock provider is probed. Call clk_set_defaults()
791 * also after the device is probed. This takes care of cases
792 * where the DT is used to setup default parents and rates
793 * using assigned-clocks
794 */
Marek Vasut05e3d8e2022-01-01 19:51:39 +0100795 clk_set_defaults(dev, CLK_DEFAULTS_POST);
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200796
797 return 0;
798}
799
Simon Glass36ad2342015-06-23 15:39:15 -0600800UCLASS_DRIVER(clk) = {
801 .id = UCLASS_CLK,
802 .name = "clk",
Jean-Jacques Hiblot9601f322019-10-22 14:00:06 +0200803 .post_probe = clk_uclass_post_probe,
Simon Glass36ad2342015-06-23 15:39:15 -0600804};