Blame - arch/x86/Kconfig - filogic/uboot

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Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	1	menu "x86 architecture"
				2	depends on X86
				3
				4	config SYS_ARCH
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	5	default "x86"
				6
Masahiro Yamada	9520b71	2014-10-24 01:30:43 +0900	[diff] [blame]	7	config USE_PRIVATE_LIBGCC
				8	default y
				9
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	10	choice
				11	prompt "Target select"
				12
				13	config TARGET_COREBOOT
				14	bool "Support coreboot"
Simon Glass	0b36ecd	2014-11-12 22:42:07 -0700	[diff] [blame]	15	help
				16	This target is used for running U-Boot on top of Coreboot. In
				17	this case Coreboot does the early inititalisation, and U-Boot
				18	takes over once the RAM, video and CPU are fully running.
				19	U-Boot is loaded as a fallback payload from Coreboot, in
				20	Coreboot terminology. This method was used for the Chromebook
				21	Pixel when launched.
				22
				23	config TARGET_CHROMEBOOK_LINK
				24	bool "Support Chromebook link"
				25	help
				26	This is the Chromebook Pixel released in 2013. It uses an Intel
				27	i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
				28	SDRAM. It has a Panther Point platform controller hub, PCIe
				29	WiFi and Bluetooth. It also includes a 720p webcam, USB SD
				30	reader, microphone and speakers, display port and 32GB SATA
				31	solid state drive. There is a Chrome OS EC connected on LPC,
				32	and it provides a 2560x1700 high resolution touch-enabled LCD
				33	display.
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	34
				35	endchoice
				36
Simon Glass	98f139b	2014-11-12 22:42:10 -0700	[diff] [blame]	37	config RAMBASE
				38	hex
				39	default 0x100000
				40
				41	config RAMTOP
				42	hex
				43	default 0x200000
				44
				45	config XIP_ROM_SIZE
				46	hex
				47	default 0x10000
				48
				49	config CPU_ADDR_BITS
				50	int
				51	default 36
				52
Simon Glass	268eefd	2014-11-12 22:42:28 -0700	[diff] [blame]	53	config HPET_ADDRESS
				54	hex
				55	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
				56
				57	config SMM_TSEG
				58	bool
				59	default n
				60
				61	config SMM_TSEG_SIZE
				62	hex
				63
Simon Glass	6622b34	2014-11-12 22:42:08 -0700	[diff] [blame]	64	config ROM_SIZE
				65	hex
				66	default 0x800000
				67
				68	config HAVE_INTEL_ME
				69	bool "Platform requires Intel Management Engine"
				70	help
				71	Newer higher-end devices have an Intel Management Engine (ME)
				72	which is a very large binary blob (typically 1.5MB) which is
				73	required for the platform to work. This enforces a particular
				74	SPI flash format. You will need to supply the me.bin file in
				75	your board directory.
				76
Simon Glass	268eefd	2014-11-12 22:42:28 -0700	[diff] [blame]	77	config X86_RAMTEST
				78	bool "Perform a simple RAM test after SDRAM initialisation"
				79	help
				80	If there is something wrong with SDRAM then the platform will
				81	often crash within U-Boot or the kernel. This option enables a
				82	very simple RAM test that quickly checks whether the SDRAM seems
				83	to work correctly. It is not exhaustive but can save time by
				84	detecting obvious failures.
				85
Simon Glass	0b36ecd	2014-11-12 22:42:07 -0700	[diff] [blame]	86	source "arch/x86/cpu/ivybridge/Kconfig"
				87
Simon Glass	26a2240	2014-11-12 22:42:29 -0700	[diff] [blame]	88	source "board/coreboot/coreboot/Kconfig"
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	89
Simon Glass	0b36ecd	2014-11-12 22:42:07 -0700	[diff] [blame]	90	source "board/google/chromebook_link/Kconfig"
				91
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	92	endmenu