Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2011 |
| 4 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
| 5 | * |
| 6 | * Copyright (C) 2009 TechNexion Ltd. |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __TAM3517_H |
| 10 | #define __TAM3517_H |
| 11 | |
| 12 | /* |
| 13 | * High Level Configuration Options |
| 14 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 15 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 16 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
Nishanth Menon | fa96c96 | 2015-03-09 17:12:04 -0500 | [diff] [blame] | 17 | #include <asm/arch/omap.h> |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 18 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 19 | /* Clock Defines */ |
| 20 | #define V_OSCK 26000000 /* Clock output from T2 */ |
| 21 | #define V_SCLK (V_OSCK >> 1) |
| 22 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 23 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 24 | #define CONFIG_SETUP_MEMORY_TAGS |
| 25 | #define CONFIG_INITRD_TAG |
| 26 | #define CONFIG_REVISION_TAG |
| 27 | |
| 28 | /* |
| 29 | * Size of malloc() pool |
| 30 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 31 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ |
| 32 | 2 * 1024 * 1024) |
| 33 | /* |
| 34 | * DDR related |
| 35 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 36 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) |
| 37 | |
| 38 | /* |
| 39 | * Hardware drivers |
| 40 | */ |
| 41 | |
| 42 | /* |
| 43 | * NS16550 Configuration |
| 44 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 45 | #define CONFIG_SYS_NS16550_SERIAL |
| 46 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 47 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
| 48 | |
| 49 | /* |
| 50 | * select serial console configuration |
| 51 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 52 | #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 53 | |
| 54 | /* allow to overwrite serial and ethaddr */ |
| 55 | #define CONFIG_ENV_OVERWRITE |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 56 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 57 | 115200} |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 58 | /* EHCI */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 59 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 60 | |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_I2C |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 62 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ |
| 63 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ |
| 64 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 65 | |
| 66 | /* |
| 67 | * Board NAND Info. |
| 68 | */ |
| 69 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ |
| 70 | /* to access */ |
| 71 | /* nand at CS0 */ |
| 72 | |
| 73 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ |
| 74 | /* NAND devices */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 75 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 76 | /* |
| 77 | * Miscellaneous configurable options |
| 78 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 79 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 80 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 81 | #define CONFIG_SYS_MAXARGS 32 /* max number of command */ |
| 82 | /* args */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 83 | /* memtest works on */ |
| 84 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) |
| 85 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
| 86 | 0x01F00000) /* 31MB */ |
| 87 | |
| 88 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ |
| 89 | /* address */ |
| 90 | |
| 91 | /* |
| 92 | * AM3517 has 12 GP timers, they can be driven by the system clock |
| 93 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
| 94 | * This rate is divided by a local divisor. |
| 95 | */ |
| 96 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 |
| 97 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 98 | |
| 99 | /* |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 100 | * Physical Memory Map |
| 101 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 102 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 103 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
| 104 | |
| 105 | /* |
| 106 | * FLASH and environment organization |
| 107 | */ |
| 108 | |
| 109 | /* **** PISMO SUPPORT *** */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 110 | |
| 111 | /* Redundant Environment */ |
| 112 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
Adam Ford | 6b1c165 | 2017-09-04 21:08:02 -0500 | [diff] [blame] | 113 | #define CONFIG_ENV_OFFSET 0x180000 |
| 114 | #define CONFIG_ENV_ADDR 0x180000 |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 115 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ |
| 116 | 2 * CONFIG_SYS_ENV_SECT_SIZE) |
| 117 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
| 118 | |
| 119 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 120 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
| 121 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 |
| 122 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 123 | CONFIG_SYS_INIT_RAM_SIZE - \ |
| 124 | GENERATED_GBL_DATA_SIZE) |
| 125 | |
| 126 | /* |
| 127 | * ethernet support, EMAC |
| 128 | * |
| 129 | */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 130 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 131 | #define CONFIG_BOOTP_DNS2 |
| 132 | #define CONFIG_BOOTP_SEND_HOSTNAME |
| 133 | #define CONFIG_NET_RETRY_COUNT 10 |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 134 | |
| 135 | /* Defines for SPL */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 136 | #define CONFIG_SPL_CONSOLE |
Jeroen Hofstee | 64407af | 2013-12-21 18:03:09 +0100 | [diff] [blame] | 137 | #define CONFIG_SPL_NAND_SOFTECC |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 138 | #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ |
| 139 | |
Scott Wood | c352a0c | 2012-09-20 19:09:07 -0500 | [diff] [blame] | 140 | #define CONFIG_SPL_NAND_BASE |
| 141 | #define CONFIG_SPL_NAND_DRIVERS |
| 142 | #define CONFIG_SPL_NAND_ECC |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 143 | |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 144 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
| 145 | CONFIG_SPL_TEXT_BASE) |
Stefano Babic | e0faf3c | 2016-06-14 09:13:37 +0200 | [diff] [blame] | 146 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 147 | |
| 148 | #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 |
| 149 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 150 | #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ |
| 151 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 152 | |
Stefano Babic | e0faf3c | 2016-06-14 09:13:37 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
| 154 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
| 155 | |
| 156 | /* FAT */ |
| 157 | #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" |
| 158 | #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" |
| 159 | |
| 160 | /* RAW SD card / eMMC */ |
| 161 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ |
| 162 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ |
| 163 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ |
| 164 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 165 | /* NAND boot config */ |
| 166 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 167 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
| 168 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 169 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 170 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 171 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
| 172 | #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ |
| 173 | 48, 49, 50, 51, 52, 53, 54, 55,\ |
| 174 | 56, 57, 58, 59, 60, 61, 62, 63} |
| 175 | #define CONFIG_SYS_NAND_ECCSIZE 256 |
| 176 | #define CONFIG_SYS_NAND_ECCBYTES 3 |
pekon gupta | 3ef4973 | 2013-11-18 19:03:01 +0530 | [diff] [blame] | 177 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 178 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 179 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
| 180 | |
| 181 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 |
| 182 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 |
| 183 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 184 | /* Setup MTD for NAND on the SOM */ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 185 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 186 | #define CONFIG_TAM3517_SETTINGS \ |
| 187 | "netdev=eth0\0" \ |
| 188 | "nandargs=setenv bootargs root=${nandroot} " \ |
| 189 | "rootfstype=${nandrootfstype}\0" \ |
| 190 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 191 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 192 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 193 | "addip_sta=setenv bootargs ${bootargs} " \ |
| 194 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 195 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 196 | "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ |
| 197 | "addip=if test -n ${ipdyn};then run addip_dyn;" \ |
| 198 | "else run addip_sta;fi\0" \ |
| 199 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
| 200 | "addtty=setenv bootargs ${bootargs}" \ |
| 201 | " console=ttyO0,${baudrate}\0" \ |
| 202 | "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ |
| 203 | "loadaddr=82000000\0" \ |
| 204 | "kernel_addr_r=82000000\0" \ |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 205 | "hostname=" CONFIG_HOSTNAME "\0" \ |
| 206 | "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 207 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
| 208 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 209 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ |
| 210 | "bootm ${kernel_addr}\0" \ |
| 211 | "nandboot=run nandargs addip addtty addmtd addmisc;" \ |
| 212 | "nand read ${kernel_addr_r} kernel\0" \ |
| 213 | "bootm ${kernel_addr_r}\0" \ |
| 214 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ |
| 215 | "run nfsargs addip addtty addmtd addmisc;" \ |
| 216 | "bootm ${kernel_addr_r}\0" \ |
| 217 | "net_self=if run net_self_load;then " \ |
| 218 | "run ramargs addip addtty addmtd addmisc;" \ |
| 219 | "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ |
| 220 | "else echo Images not loades;fi\0" \ |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 221 | "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 222 | "load=tftp ${loadaddr} ${u-boot}\0" \ |
| 223 | "loadmlo=tftp ${loadaddr} ${mlo}\0" \ |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 224 | "mlo=" CONFIG_HOSTNAME "/MLO\0" \ |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 225 | "uboot_addr=0x80000\0" \ |
| 226 | "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ |
| 227 | "nand write ${loadaddr} ${uboot_addr} 80000\0" \ |
| 228 | "updatemlo=nandecc hw;nand erase 0 20000;" \ |
| 229 | "nand write ${loadaddr} 0 20000\0" \ |
| 230 | "upd=if run load;then echo Updating u-boot;if run update;" \ |
| 231 | "then echo U-Boot updated;" \ |
| 232 | "else echo Error updating u-boot !;" \ |
| 233 | "echo Board without bootloader !!;" \ |
| 234 | "fi;" \ |
| 235 | "else echo U-Boot not downloaded..exiting;fi\0" \ |
| 236 | |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 237 | /* |
| 238 | * this is common code for all TAM3517 boards. |
| 239 | * MAC address is stored from manufacturer in |
| 240 | * I2C EEPROM |
| 241 | */ |
| 242 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 243 | /* |
| 244 | * The I2C EEPROM on the TAM3517 contains |
| 245 | * mac address and production data |
| 246 | */ |
| 247 | struct tam3517_module_info { |
| 248 | char customer[48]; |
| 249 | char product[48]; |
| 250 | |
| 251 | /* |
| 252 | * bit 0~47 : sequence number |
| 253 | * bit 48~55 : week of year, from 0. |
| 254 | * bit 56~63 : year |
| 255 | */ |
| 256 | unsigned long long sequence_number; |
| 257 | |
| 258 | /* |
| 259 | * bit 0~7 : revision fixed |
| 260 | * bit 8~15 : revision major |
| 261 | * bit 16~31 : TNxxx |
| 262 | */ |
| 263 | unsigned int revision; |
| 264 | unsigned char eth_addr[4][8]; |
| 265 | unsigned char _rev[100]; |
| 266 | }; |
| 267 | |
Stefano Babic | 0a152e6 | 2012-11-23 05:19:25 +0000 | [diff] [blame] | 268 | #define TAM3517_READ_EEPROM(info, ret) \ |
| 269 | do { \ |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 270 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 271 | if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ |
Stefano Babic | 0a152e6 | 2012-11-23 05:19:25 +0000 | [diff] [blame] | 272 | (void *)info, sizeof(*info))) \ |
| 273 | ret = 1; \ |
| 274 | else \ |
| 275 | ret = 0; \ |
| 276 | } while (0) |
| 277 | |
| 278 | #define TAM3517_READ_MAC_FROM_EEPROM(info) \ |
| 279 | do { \ |
| 280 | char buf[80], ethname[20]; \ |
| 281 | int i; \ |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 282 | memset(buf, 0, sizeof(buf)); \ |
Stefano Babic | 0a152e6 | 2012-11-23 05:19:25 +0000 | [diff] [blame] | 283 | for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 284 | sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ |
Stefano Babic | 0a152e6 | 2012-11-23 05:19:25 +0000 | [diff] [blame] | 285 | (info)->eth_addr[i][5], \ |
| 286 | (info)->eth_addr[i][4], \ |
| 287 | (info)->eth_addr[i][3], \ |
| 288 | (info)->eth_addr[i][2], \ |
| 289 | (info)->eth_addr[i][1], \ |
| 290 | (info)->eth_addr[i][0]); \ |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 291 | \ |
| 292 | if (i) \ |
| 293 | sprintf(ethname, "eth%daddr", i); \ |
| 294 | else \ |
Ben Whitten | 34fd6c9 | 2015-12-30 13:05:58 +0000 | [diff] [blame] | 295 | strcpy(ethname, "ethaddr"); \ |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 296 | printf("Setting %s from EEPROM with %s\n", ethname, buf);\ |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 297 | env_set(ethname, buf); \ |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 298 | } \ |
| 299 | } while (0) |
Stefano Babic | 0a152e6 | 2012-11-23 05:19:25 +0000 | [diff] [blame] | 300 | |
| 301 | /* The following macros are taken from Technexion's documentation */ |
| 302 | #define TAM3517_sequence_number(info) \ |
| 303 | ((info)->sequence_number % 0x1000000000000LL) |
| 304 | #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) |
| 305 | #define TAM3517_year(info) ((info)->sequence_number >> 56) |
| 306 | #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) |
| 307 | #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) |
| 308 | #define TAM3517_revision_tn(info) ((info)->revision >> 16) |
| 309 | |
| 310 | #define TAM3517_PRINT_SOM_INFO(info) \ |
| 311 | do { \ |
| 312 | printf("Vendor:%s\n", (info)->customer); \ |
| 313 | printf("SOM: %s\n", (info)->product); \ |
| 314 | printf("SeqNr: %02llu%02llu%012llu\n", \ |
| 315 | TAM3517_year(info), \ |
| 316 | TAM3517_week_of_year(info), \ |
| 317 | TAM3517_sequence_number(info)); \ |
| 318 | printf("Rev: TN%u %u.%u\n", \ |
| 319 | TAM3517_revision_tn(info), \ |
| 320 | TAM3517_revision_major(info), \ |
| 321 | TAM3517_revision_fixed(info)); \ |
| 322 | } while (0) |
| 323 | |
Stefano Babic | f39fd59 | 2012-08-29 01:21:59 +0000 | [diff] [blame] | 324 | #endif |
| 325 | |
Stefano Babic | 1f76ac1 | 2011-11-30 23:56:52 +0000 | [diff] [blame] | 326 | #endif /* __TAM3517_H */ |