Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / f7b6621c4bf8221858f6c8f18d6c0a47590cc825 / . / arch / arm / dts / k3-am625-sk-u-boot.dtsi
blob: a60c37f1dbf077b9be7d095f791267abd1c10d67 [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM625 SK dts file for SPLs
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
Neha Malcom Francis8f8f4fc2023-07-22 00:14:38 +0530[diff] [blame]7#include "k3-am625-sk-binman.dtsi"
8
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
12 tick-timer = &timer1;
13 };
14
15 aliases {
16 mmc1 = &sdhci1;
17 };
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]18
19 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]21 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]22};
23
24&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]26
27 timer1: timer@2400000 {
28 compatible = "ti,omap5430-timer";
29 reg = <0x00 0x2400000 0x00 0x80>;
30 ti,timer-alwon;
31 clock-frequency = <25000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]33 };
34};
35
36&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]38};
39
40&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]42};
43
44&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]46};
47
48&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]50};
51
52&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]54};
55
56&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]58};
59
60&wkup_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]62};
63
64&chipid {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]66};
67
68&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]70};
71
72&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]74};
75
76&main_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]78};
79
80&main_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]82};
83
84&cbass_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]86};
87
88&cbass_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]90};
91
92&mcu_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]94};
95
96&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]98};
99
100&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]102};
103
104&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]106};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]107
108&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]110};
111
112&ospi0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]114};
115
116&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]118
119 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]121
122 partitions {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]124
125 partition@3fc0000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]127 };
128 };
129 };
130};
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]131
132&cpsw3g {
133 reg = <0x0 0x8000000 0x0 0x200000>,
134 <0x0 0x43000200 0x0 0x8>;
135 reg-names = "cpsw_nuss", "mac_efuse";
136 /delete-property/ ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]138
139 cpsw-phy-sel@04044 {
140 compatible = "ti,am64-phy-gmii-sel";
141 reg = <0x0 0x00104044 0x0 0x8>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]142 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]143 };
144};
145
146&cpsw_port1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]148};
149
150&cpsw_port2 {
151 status = "disabled";
152};