| Dominic Rath | 11147e0 | 2021-12-22 08:57:46 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * TI DP83869 PHY drivers |
| 4 | * |
| 5 | */ |
| 6 | |
| 7 | #ifndef _DT_BINDINGS_TI_DP83869_H |
| 8 | #define _DT_BINDINGS_TI_DP83869_H |
| 9 | |
| 10 | /* PHY CTRL bits */ |
| 11 | #define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 |
| 12 | #define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 |
| 13 | #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 |
| 14 | #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 |
| 15 | |
| 16 | /* RGMIIDCTL internal delay for rx and tx */ |
| 17 | #define DP83869_RGMIIDCTL_250_PS 0x0 |
| 18 | #define DP83869_RGMIIDCTL_500_PS 0x1 |
| 19 | #define DP83869_RGMIIDCTL_750_PS 0x2 |
| 20 | #define DP83869_RGMIIDCTL_1_NS 0x3 |
| 21 | #define DP83869_RGMIIDCTL_1_25_NS 0x4 |
| 22 | #define DP83869_RGMIIDCTL_1_50_NS 0x5 |
| 23 | #define DP83869_RGMIIDCTL_1_75_NS 0x6 |
| 24 | #define DP83869_RGMIIDCTL_2_00_NS 0x7 |
| 25 | #define DP83869_RGMIIDCTL_2_25_NS 0x8 |
| 26 | #define DP83869_RGMIIDCTL_2_50_NS 0x9 |
| 27 | #define DP83869_RGMIIDCTL_2_75_NS 0xa |
| 28 | #define DP83869_RGMIIDCTL_3_00_NS 0xb |
| 29 | #define DP83869_RGMIIDCTL_3_25_NS 0xc |
| 30 | #define DP83869_RGMIIDCTL_3_50_NS 0xd |
| 31 | #define DP83869_RGMIIDCTL_3_75_NS 0xe |
| 32 | #define DP83869_RGMIIDCTL_4_00_NS 0xf |
| 33 | |
| 34 | /* IO_MUX_CFG - Clock output selection */ |
| 35 | #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 |
| 36 | #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 |
| 37 | #define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 |
| 38 | #define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 |
| 39 | #define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 |
| 40 | #define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 |
| 41 | #define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 |
| 42 | #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 |
| 43 | #define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 |
| 44 | #define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 |
| 45 | #define DP83869_CLK_O_SEL_CHN_C_TCLK 0xA |
| 46 | #define DP83869_CLK_O_SEL_CHN_D_TCLK 0xB |
| 47 | #define DP83869_CLK_O_SEL_REF_CLK 0xC |
| 48 | /* Special flag to indicate clock should be off */ |
| 49 | #define DP83869_CLK_O_SEL_OFF 0xFFFFFFFF |
| 50 | |
| 51 | /* OPMODE - Operation mode */ |
| 52 | #define DP83869_RGMII_COPPER_ETHERNET 0x00 |
| 53 | #define DP83869_RGMII_1000_BASE 0x01 |
| 54 | #define DP83869_RGMII_100_BASE 0x02 |
| 55 | #define DP83869_RGMII_SGMII_BRIDGE 0x03 |
| 56 | #define DP83869_1000M_MEDIA_CONVERT 0x04 |
| 57 | #define DP83869_100M_MEDIA_CONVERT 0x05 |
| 58 | #define DP83869_SGMII_COPPER_ETHERNET 0x06 |
| 59 | |
| 60 | #endif |