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git01.mediatek.com / filogic / uboot / f78eff68ef5da51f78582c4177ed824057bfe38f / . / drivers / clk / uniphier / clk-uniphier-sys.c
blob: 3b8595fe610a9fdf4618e9de4afd8a528c5946c8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada644f5bf2017-08-29 01:06:15 +0900[diff] [blame]2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada644f5bf2017-08-29 01:06:15 +0900[diff] [blame]5 */
6
7#include "clk-uniphier.h"
8
Masahiro Yamada5d15b732017-10-14 02:21:19 +0900[diff] [blame]9#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
Masahiro Yamadacdc6f652018-12-19 20:03:20 +0900[diff] [blame]10 UNIPHIER_CLK_RATE(128, 50000000), \
Masahiro Yamada5d15b732017-10-14 02:21:19 +0900[diff] [blame]11 UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
12
13#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \
Masahiro Yamadacdc6f652018-12-19 20:03:20 +0900[diff] [blame]14 UNIPHIER_CLK_RATE(128, 50000000), \
Masahiro Yamada5d15b732017-10-14 02:21:19 +0900[diff] [blame]15 UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
16
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]17const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
18#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
19 defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
20 defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
Masahiro Yamadaec4f6ba2019-07-10 20:07:35 +0900[diff] [blame]21 UNIPHIER_LD4_SYS_CLK_NAND(2), /* nand */
22 UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
Kunihiko Hayashicb2f1d92018-04-18 10:05:33 +0900[diff] [blame]23 UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
24 UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]25 UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
Kunihiko Hayashicb2f1d92018-04-18 10:05:33 +0900[diff] [blame]26 UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]27 UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
28 UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
29 UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
30 UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */
Kunihiko Hayashi5f9a8712023-02-20 14:50:31 +0900[diff] [blame]31 UNIPHIER_CLK_RATE(17, 25000000), /* usb30-phy2 (PXs2) */
32 UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy3 (PXs2) */
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]33 UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */
Kunihiko Hayashi5f9a8712023-02-20 14:50:31 +0900[diff] [blame]34 UNIPHIER_CLK_RATE(21, 25000000), /* usb31-phy2 (PXs2) */
Kunihiko Hayashi04f19712021-07-06 19:01:06 +0900[diff] [blame]35 UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2), /* pcie (Pro5) */
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]36 { /* sentinel */ }
37#endif
Masahiro Yamada644f5bf2017-08-29 01:06:15 +0900[diff] [blame]38};
39
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]40const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
41#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
Masahiro Yamadaec4f6ba2019-07-10 20:07:35 +0900[diff] [blame]42 UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */
43 UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
44 UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */
Kunihiko Hayashicb2f1d92018-04-18 10:05:33 +0900[diff] [blame]45 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]46 UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
47 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
48 UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
49 UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
Kunihiko Hayashi5f9a8712023-02-20 14:50:31 +0900[diff] [blame]50 UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy2 (LD20) */
51 UNIPHIER_CLK_RATE(19, 25000000), /* usb30-phy3 (LD20) */
Kunihiko Hayashi04f19712021-07-06 19:01:06 +0900[diff] [blame]52 UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4), /* pcie */
Masahiro Yamada49806682017-10-13 19:21:59 +0900[diff] [blame]53 { /* sentinel */ }
54#endif
Masahiro Yamada644f5bf2017-08-29 01:06:15 +0900[diff] [blame]55};
Masahiro Yamada52cdec02017-10-13 19:22:00 +0900[diff] [blame]56
57const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
58#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
Masahiro Yamadaec4f6ba2019-07-10 20:07:35 +0900[diff] [blame]59 UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */
60 UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
61 UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */
Kunihiko Hayashicb2f1d92018-04-18 10:05:33 +0900[diff] [blame]62 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
63 UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
Masahiro Yamada52cdec02017-10-13 19:22:00 +0900[diff] [blame]64 UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
65 UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
66 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
67 UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16), /* usb30-phy0 */
68 UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18), /* usb30-phy1 */
69 UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */
70 UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */
71 UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */
Kunihiko Hayashi04f19712021-07-06 19:01:06 +0900[diff] [blame]72 UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 3), /* pcie */
Masahiro Yamada52cdec02017-10-13 19:22:00 +0900[diff] [blame]73 { /* sentinel */ }
74#endif
75};