blob: 361871525ef5c48b8b700be3749e6262af4fd34e [file] [log] [blame]
Peng Fanf7765d72017-02-22 16:21:56 +08001/*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/sys_proto.h>
10#include <asm/arch/mx7ulp-pins.h>
11#include <asm/arch/iomux.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
15#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
16
17int dram_init(void)
18{
19 gd->ram_size = PHYS_SDRAM_SIZE;
20
21 return 0;
22}
23
24static iomux_cfg_t const lpuart4_pads[] = {
25 MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
26 MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
27};
28
29static void setup_iomux_uart(void)
30{
31 mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
32 ARRAY_SIZE(lpuart4_pads));
33}
34
35int board_early_init_f(void)
36{
37 setup_iomux_uart();
38
39 return 0;
40}
41
42int board_init(void)
43{
44 /* address of boot parameters */
45 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
46
47 return 0;
48}