| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Nishanth Menon | ad63dd7 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 2 | /* |
| 3 | * ti_armv7_omap.h |
| 4 | * |
| Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/ |
| Nishanth Menon | ad63dd7 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 6 | * |
| Nishanth Menon | ad63dd7 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 7 | * The various ARMv7 SoCs from TI all share a number of IP blocks when |
| 8 | * implementing a given feature. This is meant to isolate the features |
| 9 | * that are based on OMAP architecture. |
| 10 | */ |
| 11 | #ifndef __CONFIG_TI_ARMV7_OMAP_H__ |
| 12 | #define __CONFIG_TI_ARMV7_OMAP_H__ |
| 13 | |
| Nishanth Menon | ad63dd7 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 14 | /* |
| 15 | * GPMC NAND block. We support 1 device and the physical address to |
| 16 | * access CS0 at is 0x8000000. |
| 17 | */ |
| Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 18 | #ifdef CONFIG_MTD_RAW_NAND |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 19 | #ifndef CFG_SYS_NAND_BASE |
| 20 | #define CFG_SYS_NAND_BASE 0x8000000 |
| Nishanth Menon | ad63dd7 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 21 | #endif |
| Nishanth Menon | ad63dd7 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 22 | #endif |
| 23 | |
| 24 | /* Now for the remaining common defines */ |
| 25 | #include <configs/ti_armv7_common.h> |
| 26 | |
| 27 | #endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ |