Robert Beckett | f746ab6 | 2019-11-12 19:15:11 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * Copyright 2015 Timesys Corporation. |
| 4 | * Copyright 2015 General Electric Company |
| 5 | * |
| 6 | * This file is dual-licensed: you can use it either under the terms |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual |
| 8 | * licensing only applies to this file, and not this project as a |
| 9 | * whole. |
| 10 | * |
| 11 | * a) This file is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License |
| 13 | * version 2 as published by the Free Software Foundation. |
| 14 | * |
| 15 | * This file is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * Or, alternatively, |
| 21 | * |
| 22 | * b) Permission is hereby granted, free of charge, to any person |
| 23 | * obtaining a copy of this software and associated documentation |
| 24 | * files (the "Software"), to deal in the Software without |
| 25 | * restriction, including without limitation the rights to use, |
| 26 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 27 | * sell copies of the Software, and to permit persons to whom the |
| 28 | * Software is furnished to do so, subject to the following |
| 29 | * conditions: |
| 30 | * |
| 31 | * The above copyright notice and this permission notice shall be |
| 32 | * included in all copies or substantial portions of the Software. |
| 33 | * |
| 34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 41 | * OTHER DEALINGS IN THE SOFTWARE. |
| 42 | */ |
| 43 | |
| 44 | /dts-v1/; |
| 45 | |
| 46 | #include "imx6q-bx50v3.dtsi" |
| 47 | |
| 48 | / { |
| 49 | model = "General Electric B850v3"; |
| 50 | compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q"; |
| 51 | |
| 52 | chosen { |
| 53 | stdout-path = &uart3; |
| 54 | }; |
| 55 | }; |
| 56 | |
| 57 | &clks { |
| 58 | assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| 59 | <&clks IMX6QDL_CLK_LDB_DI1_SEL>, |
| 60 | <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, |
| 61 | <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; |
| 62 | assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, |
| 63 | <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, |
| 64 | <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, |
| 65 | <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; |
| 66 | }; |
| 67 | |
| 68 | &ldb { |
| 69 | fsl,dual-channel; |
| 70 | status = "okay"; |
| 71 | |
| 72 | lvds0: lvds-channel@0 { |
| 73 | fsl,data-mapping = "spwg"; |
| 74 | fsl,data-width = <24>; |
| 75 | status = "okay"; |
| 76 | |
| 77 | port@4 { |
| 78 | reg = <4>; |
| 79 | |
| 80 | lvds0_out: endpoint { |
| 81 | remote-endpoint = <&stdp4028_in>; |
| 82 | }; |
| 83 | }; |
| 84 | }; |
| 85 | }; |
| 86 | |
| 87 | &i2c2 { |
| 88 | pca9547_ddc: mux@70 { |
| 89 | compatible = "nxp,pca9547"; |
| 90 | reg = <0x70>; |
| 91 | #address-cells = <1>; |
| 92 | #size-cells = <0>; |
| 93 | |
| 94 | mux2_i2c1: i2c@0 { |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <0>; |
| 97 | reg = <0x0>; |
| 98 | }; |
| 99 | |
| 100 | mux2_i2c2: i2c@1 { |
| 101 | #address-cells = <1>; |
| 102 | #size-cells = <0>; |
| 103 | reg = <0x1>; |
| 104 | }; |
| 105 | |
| 106 | mux2_i2c3: i2c@2 { |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <0>; |
| 109 | reg = <0x2>; |
| 110 | }; |
| 111 | |
| 112 | mux2_i2c4: i2c@3 { |
| 113 | #address-cells = <1>; |
| 114 | #size-cells = <0>; |
| 115 | reg = <0x3>; |
| 116 | }; |
| 117 | |
| 118 | mux2_i2c5: i2c@4 { |
| 119 | #address-cells = <1>; |
| 120 | #size-cells = <0>; |
| 121 | reg = <0x4>; |
| 122 | }; |
| 123 | |
| 124 | mux2_i2c6: i2c@5 { |
| 125 | #address-cells = <1>; |
| 126 | #size-cells = <0>; |
| 127 | reg = <0x5>; |
| 128 | }; |
| 129 | |
| 130 | mux2_i2c7: i2c@6 { |
| 131 | #address-cells = <1>; |
| 132 | #size-cells = <0>; |
| 133 | reg = <0x6>; |
| 134 | }; |
| 135 | |
| 136 | mux2_i2c8: i2c@7 { |
| 137 | #address-cells = <1>; |
| 138 | #size-cells = <0>; |
| 139 | reg = <0x7>; |
| 140 | }; |
| 141 | }; |
| 142 | }; |
| 143 | |
| 144 | &hdmi { |
| 145 | ddc-i2c-bus = <&mux2_i2c1>; |
| 146 | }; |
| 147 | |
| 148 | &mux1_i2c1 { |
| 149 | ads7830@4a { |
| 150 | compatible = "ti,ads7830"; |
| 151 | reg = <0x4a>; |
| 152 | }; |
| 153 | }; |
| 154 | |
| 155 | &mux2_i2c2 { |
| 156 | clock-frequency = <100000>; |
| 157 | |
| 158 | stdp2690@72 { |
| 159 | compatible = "megachips,stdp2690-ge-b850v3-fw"; |
| 160 | reg = <0x72>; |
| 161 | |
| 162 | ports { |
| 163 | #address-cells = <1>; |
| 164 | #size-cells = <0>; |
| 165 | |
| 166 | port@0 { |
| 167 | reg = <0>; |
| 168 | |
| 169 | stdp2690_in: endpoint { |
| 170 | remote-endpoint = <&stdp4028_out>; |
| 171 | }; |
| 172 | }; |
| 173 | |
| 174 | port@1 { |
| 175 | reg = <1>; |
| 176 | |
| 177 | stdp2690_out: endpoint { |
| 178 | /* Connector for external display */ |
| 179 | }; |
| 180 | }; |
| 181 | }; |
| 182 | }; |
| 183 | |
| 184 | stdp4028@73 { |
| 185 | compatible = "megachips,stdp4028-ge-b850v3-fw"; |
| 186 | reg = <0x73>; |
| 187 | interrupt-parent = <&gpio2>; |
| 188 | interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; |
| 189 | |
| 190 | ports { |
| 191 | #address-cells = <1>; |
| 192 | #size-cells = <0>; |
| 193 | |
| 194 | port@0 { |
| 195 | reg = <0>; |
| 196 | |
| 197 | stdp4028_in: endpoint { |
| 198 | remote-endpoint = <&lvds0_out>; |
| 199 | }; |
| 200 | }; |
| 201 | |
| 202 | port@1 { |
| 203 | reg = <1>; |
| 204 | |
| 205 | stdp4028_out: endpoint { |
| 206 | remote-endpoint = <&stdp2690_in>; |
| 207 | }; |
| 208 | }; |
| 209 | }; |
| 210 | }; |
| 211 | }; |
| 212 | |
| 213 | &pca9539 { |
| 214 | P10 { |
| 215 | gpio-hog; |
| 216 | gpios = <8 0>; |
| 217 | output-low; |
| 218 | line-name = "PCA9539-P10"; |
| 219 | }; |
| 220 | |
| 221 | P11 { |
| 222 | gpio-hog; |
| 223 | gpios = <9 0>; |
| 224 | output-low; |
| 225 | line-name = "PCA9539-P11"; |
| 226 | }; |
| 227 | }; |
| 228 | |
| 229 | &pci_root { |
| 230 | /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ |
| 231 | bridge@1,0 { |
| 232 | compatible = "pci10b5,8605"; |
| 233 | reg = <0x00010000 0 0 0 0>; |
| 234 | |
| 235 | #address-cells = <3>; |
| 236 | #size-cells = <2>; |
| 237 | #interrupt-cells = <1>; |
| 238 | |
| 239 | bridge@2,1 { |
| 240 | compatible = "pci10b5,8605"; |
| 241 | reg = <0x00020800 0 0 0 0>; |
| 242 | |
| 243 | #address-cells = <3>; |
| 244 | #size-cells = <2>; |
| 245 | #interrupt-cells = <1>; |
| 246 | |
| 247 | /* Intel Corporation I210 Gigabit Network Connection */ |
| 248 | ethernet@3,0 { |
| 249 | compatible = "pci8086,1533"; |
| 250 | reg = <0x00030000 0 0 0 0>; |
| 251 | }; |
| 252 | }; |
| 253 | |
| 254 | bridge@2,2 { |
| 255 | compatible = "pci10b5,8605"; |
| 256 | reg = <0x00021000 0 0 0 0>; |
| 257 | |
| 258 | #address-cells = <3>; |
| 259 | #size-cells = <2>; |
| 260 | #interrupt-cells = <1>; |
| 261 | |
| 262 | /* Intel Corporation I210 Gigabit Network Connection */ |
| 263 | switch_nic: ethernet@4,0 { |
| 264 | compatible = "pci8086,1533"; |
| 265 | reg = <0x00040000 0 0 0 0>; |
| 266 | }; |
| 267 | }; |
| 268 | }; |
| 269 | }; |
| 270 | |
| 271 | &switch_ports { |
| 272 | port@0 { |
| 273 | reg = <0>; |
| 274 | label = "eneport1"; |
| 275 | phy-handle = <&switchphy0>; |
| 276 | }; |
| 277 | |
| 278 | port@1 { |
| 279 | reg = <1>; |
| 280 | label = "eneport2"; |
| 281 | phy-handle = <&switchphy1>; |
| 282 | }; |
| 283 | |
| 284 | port@2 { |
| 285 | reg = <2>; |
| 286 | label = "enix"; |
| 287 | phy-handle = <&switchphy2>; |
| 288 | }; |
| 289 | |
| 290 | port@3 { |
| 291 | reg = <3>; |
| 292 | label = "enid"; |
| 293 | phy-handle = <&switchphy3>; |
| 294 | }; |
| 295 | |
| 296 | port@4 { |
| 297 | reg = <4>; |
| 298 | label = "cpu"; |
| 299 | ethernet = <&switch_nic>; |
| 300 | phy-handle = <&switchphy4>; |
| 301 | }; |
| 302 | }; |