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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk7ac16102004-08-01 22:48:16 +00002/*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
10 *
11 * (C) Copyright 2002
Detlev Zundelf1b3f2b2009-05-13 10:54:10 +020012 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
wdenk7ac16102004-08-01 22:48:16 +000013 */
14
15#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -070016#include <cpu_func.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070017#include <time.h>
wdenk7ac16102004-08-01 22:48:16 +000018#if defined (CONFIG_IMX)
19
wdenk7ac16102004-08-01 22:48:16 +000020#include <asm/arch/imx-regs.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
wdenk7ac16102004-08-01 22:48:16 +000022
Jean-Christophe PLAGNIOL-VILLARD8c9fc002009-05-15 23:47:02 +020023int timer_init (void)
wdenk7ac16102004-08-01 22:48:16 +000024{
25 int i;
26 /* setup GP Timer 1 */
27 TCTL1 = TCTL_SWR;
28 for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
29 TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
30 TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
31
Graeme Russ944a7fe2011-07-15 02:21:14 +000032 /* Reset the timer */
33 TCTL1 &= ~TCTL_TEN;
34 TCTL1 |= TCTL_TEN; /* Enable timer */
wdenk7ac16102004-08-01 22:48:16 +000035
36 return (0);
37}
38
39/*
40 * timer without interrupts
41 */
Patrick Delaunay9858a602018-10-05 11:33:52 +020042static ulong get_timer_masked (void)
wdenk7ac16102004-08-01 22:48:16 +000043{
Patrick Delaunay9858a602018-10-05 11:33:52 +020044 return TCN1;
wdenk7ac16102004-08-01 22:48:16 +000045}
46
Patrick Delaunay9858a602018-10-05 11:33:52 +020047ulong get_timer (ulong base)
wdenk7ac16102004-08-01 22:48:16 +000048{
Patrick Delaunay9858a602018-10-05 11:33:52 +020049 return get_timer_masked() - base;
wdenk7ac16102004-08-01 22:48:16 +000050}
51
Simon Glassdbd79542020-05-10 11:40:11 -060052void __udelay(unsigned long usec)
wdenk7ac16102004-08-01 22:48:16 +000053{
wdenk7af1f9d2005-04-04 12:08:28 +000054 ulong endtime = get_timer_masked() + usec;
55 signed long diff;
wdenk7ac16102004-08-01 22:48:16 +000056
wdenk7af1f9d2005-04-04 12:08:28 +000057 do {
58 ulong now = get_timer_masked ();
59 diff = endtime - now;
60 } while (diff >= 0);
wdenk7ac16102004-08-01 22:48:16 +000061}
62
wdenk7ac16102004-08-01 22:48:16 +000063/*
64 * This function is derived from PowerPC code (read timebase as long long).
65 * On ARM it just returns the timer value.
66 */
67unsigned long long get_ticks(void)
68{
69 return get_timer(0);
70}
71
72/*
73 * This function is derived from PowerPC code (timebase clock frequency).
74 * On ARM it returns the number of timer ticks per second.
75 */
Simon Glassa9dc0682019-12-28 10:44:59 -070076ulong get_tbclk(void)
wdenk7ac16102004-08-01 22:48:16 +000077{
Masahiro Yamada04cfea52016-09-06 22:17:38 +090078 return CONFIG_SYS_HZ;
wdenk7ac16102004-08-01 22:48:16 +000079}
80
wdenk915b3762005-04-05 22:30:50 +000081/*
82 * Reset the cpu by setting up the watchdog timer and let him time out
83 */
Harald Seiler6f14d5f2020-12-15 16:47:52 +010084void reset_cpu(void)
wdenk915b3762005-04-05 22:30:50 +000085{
86 /* Disable watchdog and set Time-Out field to 0 */
87 WCR = 0x00000000;
88
89 /* Write Service Sequence */
90 WSR = 0x00005555;
91 WSR = 0x0000AAAA;
92
93 /* Enable watchdog */
94 WCR = 0x00000001;
95
96 while (1);
97 /*NOTREACHED*/
98}
99
wdenk7ac16102004-08-01 22:48:16 +0000100#endif /* defined (CONFIG_IMX) */