Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 5 | * Marius Groeger <mgroeger@sysgo.de> |
| 6 | * |
| 7 | * (C) Copyright 2002 |
| 8 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 9 | * Alex Zuepke <azu@sysgo.de> |
| 10 | * |
| 11 | * (C) Copyright 2002 |
Detlev Zundel | f1b3f2b | 2009-05-13 10:54:10 +0200 | [diff] [blame] | 12 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 16 | #include <cpu_func.h> |
Simon Glass | 495a5dc | 2019-11-14 12:57:30 -0700 | [diff] [blame] | 17 | #include <time.h> |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 18 | #if defined (CONFIG_IMX) |
| 19 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 20 | #include <asm/arch/imx-regs.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 21 | #include <linux/delay.h> |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 22 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c9fc00 | 2009-05-15 23:47:02 +0200 | [diff] [blame] | 23 | int timer_init (void) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 24 | { |
| 25 | int i; |
| 26 | /* setup GP Timer 1 */ |
| 27 | TCTL1 = TCTL_SWR; |
| 28 | for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ |
| 29 | TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ |
| 30 | TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ |
| 31 | |
Graeme Russ | 944a7fe | 2011-07-15 02:21:14 +0000 | [diff] [blame] | 32 | /* Reset the timer */ |
| 33 | TCTL1 &= ~TCTL_TEN; |
| 34 | TCTL1 |= TCTL_TEN; /* Enable timer */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 35 | |
| 36 | return (0); |
| 37 | } |
| 38 | |
| 39 | /* |
| 40 | * timer without interrupts |
| 41 | */ |
Patrick Delaunay | 9858a60 | 2018-10-05 11:33:52 +0200 | [diff] [blame] | 42 | static ulong get_timer_masked (void) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 43 | { |
Patrick Delaunay | 9858a60 | 2018-10-05 11:33:52 +0200 | [diff] [blame] | 44 | return TCN1; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 45 | } |
| 46 | |
Patrick Delaunay | 9858a60 | 2018-10-05 11:33:52 +0200 | [diff] [blame] | 47 | ulong get_timer (ulong base) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 48 | { |
Patrick Delaunay | 9858a60 | 2018-10-05 11:33:52 +0200 | [diff] [blame] | 49 | return get_timer_masked() - base; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 50 | } |
| 51 | |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 52 | void __udelay(unsigned long usec) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 53 | { |
wdenk | 7af1f9d | 2005-04-04 12:08:28 +0000 | [diff] [blame] | 54 | ulong endtime = get_timer_masked() + usec; |
| 55 | signed long diff; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 56 | |
wdenk | 7af1f9d | 2005-04-04 12:08:28 +0000 | [diff] [blame] | 57 | do { |
| 58 | ulong now = get_timer_masked (); |
| 59 | diff = endtime - now; |
| 60 | } while (diff >= 0); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 61 | } |
| 62 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 63 | /* |
| 64 | * This function is derived from PowerPC code (read timebase as long long). |
| 65 | * On ARM it just returns the timer value. |
| 66 | */ |
| 67 | unsigned long long get_ticks(void) |
| 68 | { |
| 69 | return get_timer(0); |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * This function is derived from PowerPC code (timebase clock frequency). |
| 74 | * On ARM it returns the number of timer ticks per second. |
| 75 | */ |
Simon Glass | a9dc068 | 2019-12-28 10:44:59 -0700 | [diff] [blame] | 76 | ulong get_tbclk(void) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 77 | { |
Masahiro Yamada | 04cfea5 | 2016-09-06 22:17:38 +0900 | [diff] [blame] | 78 | return CONFIG_SYS_HZ; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 79 | } |
| 80 | |
wdenk | 915b376 | 2005-04-05 22:30:50 +0000 | [diff] [blame] | 81 | /* |
| 82 | * Reset the cpu by setting up the watchdog timer and let him time out |
| 83 | */ |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 84 | void reset_cpu(void) |
wdenk | 915b376 | 2005-04-05 22:30:50 +0000 | [diff] [blame] | 85 | { |
| 86 | /* Disable watchdog and set Time-Out field to 0 */ |
| 87 | WCR = 0x00000000; |
| 88 | |
| 89 | /* Write Service Sequence */ |
| 90 | WSR = 0x00005555; |
| 91 | WSR = 0x0000AAAA; |
| 92 | |
| 93 | /* Enable watchdog */ |
| 94 | WCR = 0x00000001; |
| 95 | |
| 96 | while (1); |
| 97 | /*NOTREACHED*/ |
| 98 | } |
| 99 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 100 | #endif /* defined (CONFIG_IMX) */ |