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git01.mediatek.com / filogic / uboot / f70cbb2a5230eefb0a837de9542da340c4a3cc32 / . / include / asm-arm / arch-arm720t / netarm_gen_module.h
blob: 90d9da817461ce815360cff16c2d97435f40061e [file] [log] [blame]
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]1/*
2 * include/asm-armnommu/arch-netarm/netarm_gen_module.h
3 *
4 * Copyright (C) 2000, 2001 NETsilicon, Inc.
5 * Copyright (C) 2000, 2001 Red Hat, Inc.
6 *
7 * This software is copyrighted by Red Hat. LICENSEE agrees that
8 * it will not delete this copyright notice, trademarks or protective
9 * notices from any copy made by LICENSEE.
10 *
11 * This software is provided "AS-IS" and any express or implied
12 * warranties or conditions, including but not limited to any
13 * implied warranties of merchantability and fitness for a particular
14 * purpose regarding this software. In no event shall Red Hat
15 * be liable for any indirect, consequential, or incidental damages,
16 * loss of profits or revenue, loss of use or data, or interruption
17 * of business, whether the alleged damages are labeled in contract,
18 * tort, or indemnity.
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * author(s) : Joe deBlaquiere
30 */
31
32#ifndef __NETARM_GEN_MODULE_REGISTERS_H
33#define __NETARM_GEN_MODULE_REGISTERS_H
34
35/* GEN unit register offsets */
36
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]37#define NETARM_GEN_MODULE_BASE (0xFFB00000)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]38
39#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
40
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]41#define NETARM_GEN_SYSTEM_CONTROL (0x00)
42#define NETARM_GEN_STATUS_CONTROL (0x04)
43#define NETARM_GEN_PLL_CONTROL (0x08)
44#define NETARM_GEN_SOFTWARE_SERVICE (0x0c)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]45
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]46#define NETARM_GEN_TIMER1_CONTROL (0x10)
47#define NETARM_GEN_TIMER1_STATUS (0x14)
48#define NETARM_GEN_TIMER2_CONTROL (0x18)
49#define NETARM_GEN_TIMER2_STATUS (0x1c)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]50
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]51#define NETARM_GEN_PORTA (0x20)
52#define NETARM_GEN_PORTB (0x24)
53#define NETARM_GEN_PORTC (0x28)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]54
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]55#define NETARM_GEN_INTR_ENABLE (0x30)
56#define NETARM_GEN_INTR_ENABLE_SET (0x34)
57#define NETARM_GEN_INTR_ENABLE_CLR (0x38)
58#define NETARM_GEN_INTR_STATUS_EN (0x34)
59#define NETARM_GEN_INTR_STATUS_RAW (0x38)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]60
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]61#define NETARM_GEN_CACHE_CONTROL1 (0x40)
62#define NETARM_GEN_CACHE_CONTROL2 (0x44)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]63
64/* select bitfield definitions */
65
66/* System Control Register ( 0xFFB0_0000 ) */
67
68#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000)
69#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000)
70
71#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000)
72#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000)
73#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000)
74
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]75#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]76
77#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000)
78#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000)
79#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000)
80#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000)
81#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000)
82#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000)
83#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000)
84#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000)
85
86#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000)
87#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000)
88#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000)
89#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000)
90#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000)
91
92#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000)
93#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000)
94
95#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000)
96#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000)
97
98#define NETARM_GEN_SYS_CFG_DMATST (0x00001000)
99
100#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800)
101
102#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400)
103
104#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200)
105
106#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100)
107
108#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080)
109
110/* PLL Control Register ( 0xFFB0_0008 ) */
111
112#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000)
113
114#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]115 NETARM_GEN_PLL_CTL_PLLCNT_MASK)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]116
117/* Defaults for POLTST and ICP Fields in PLL CTL */
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]118#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x)
119#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6)
120#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00)
121#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]122
123
124/* Software Service Register ( 0xFFB0_000C ) */
125
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]126#define NETARM_GEN_SW_SVC_RESETA (0x123)
127#define NETARM_GEN_SW_SVC_RESETB (0x321)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]128
129/* PORT C Register ( 0xFFB0_0028 ) */
130
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]131#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00))
132#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00))
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]133
134/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
135
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]136#define NETARM_GEN_TCTL_ENABLE (0x80000000)
137#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]138
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]139#define NETARM_GEN_TCTL_USE_IRQ (0x00000000)
140#define NETARM_GEN_TCTL_USE_FIQ (0x20000000)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]141
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]142#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000)
143#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]144
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]145#define NETARM_GEN_TSTAT_INTPEN (0x40000000)
146#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF)
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]147
148/* prescale to msecs conversion */
149
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]150#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \
151 NETARM_GEN_TSTAT_CTC_MASK ) + \
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]152 1 ) ) / (NETARM_XTAL_FREQ/1000) )
153
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]154#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]155 NETARM_GEN_TSTAT_CTC_MASK ) | \
156 NETARM_GEN_TCTL_USE_PRESCALE )
157
158#if 0
159/* ifdef CONFIG_NETARM_PLL_BYPASS else */
160#error test
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]161#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \
162 NETARM_GEN_TSTAT_CTC_MASK ) + \
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]163 1 ) ) / (NETARM_XTAL_FREQ/1000) )
164
wdenkf70cbb22004-02-23 20:48:38 +0000[diff] [blame^]165#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
wdenk2ebee312004-02-23 19:30:57 +0000[diff] [blame]166 NETARM_GEN_TSTAT_CTC_MASK ) | \
167 NETARM_GEN_TCTL_USE_PRESCALE )
168#endif
169
170#endif