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Kumar Gala124b0822008-08-26 15:01:29 -05001/*
Kumar Galaf582d982011-01-09 14:06:28 -06002 * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
Kumar Gala124b0822008-08-26 15:01:29 -05003 *
Dave Liu707aa5c2010-03-05 12:22:00 +08004 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
Kumar Gala124b0822008-08-26 15:01:29 -05008 */
9
10#include <common.h>
Kumar Gala64042092010-07-14 10:04:21 -050011#include <hwconfig.h>
Kumar Gala124b0822008-08-26 15:01:29 -050012#include <asm/fsl_ddr_sdram.h>
13
14#include "ddr.h"
15
Kumar Gala72301602011-01-09 11:37:00 -060016/*
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
21 */
22#define HWCONFIG_BUFFER_SIZE 128
23
Kumar Gala124b0822008-08-26 15:01:29 -050024/* Board-specific functions defined in each board's ddr.c */
25extern void fsl_ddr_board_options(memctl_options_t *popts,
Haiying Wangfa440362008-10-03 12:36:55 -040026 dimm_params_t *pdimm,
Kumar Gala124b0822008-08-26 15:01:29 -050027 unsigned int ctrl_num);
28
York Sun454f5072011-08-26 11:32:43 -070029struct dynamic_odt {
York Sunba0c2eb2011-01-10 12:03:00 +000030 unsigned int odt_rd_cfg;
31 unsigned int odt_wr_cfg;
32 unsigned int odt_rtt_norm;
33 unsigned int odt_rtt_wr;
York Sun454f5072011-08-26 11:32:43 -070034};
York Sunba0c2eb2011-01-10 12:03:00 +000035
York Sun454f5072011-08-26 11:32:43 -070036#ifdef CONFIG_FSL_DDR3
37static const struct dynamic_odt single_Q[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +000038 { /* cs0 */
39 FSL_DDR_ODT_NEVER,
40 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
41 DDR3_RTT_20_OHM,
42 DDR3_RTT_120_OHM
43 },
44 { /* cs1 */
45 FSL_DDR_ODT_NEVER,
46 FSL_DDR_ODT_NEVER, /* tied high */
47 DDR3_RTT_OFF,
48 DDR3_RTT_120_OHM
49 },
50 { /* cs2 */
51 FSL_DDR_ODT_NEVER,
52 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
53 DDR3_RTT_20_OHM,
54 DDR3_RTT_120_OHM
55 },
56 { /* cs3 */
57 FSL_DDR_ODT_NEVER,
58 FSL_DDR_ODT_NEVER, /* tied high */
59 DDR3_RTT_OFF,
60 DDR3_RTT_120_OHM
61 }
62};
63
York Sun454f5072011-08-26 11:32:43 -070064static const struct dynamic_odt single_D[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +000065 { /* cs0 */
66 FSL_DDR_ODT_NEVER,
67 FSL_DDR_ODT_ALL,
68 DDR3_RTT_40_OHM,
69 DDR3_RTT_OFF
70 },
71 { /* cs1 */
72 FSL_DDR_ODT_NEVER,
73 FSL_DDR_ODT_NEVER,
74 DDR3_RTT_OFF,
75 DDR3_RTT_OFF
76 },
77 {0, 0, 0, 0},
78 {0, 0, 0, 0}
79};
80
York Sun454f5072011-08-26 11:32:43 -070081static const struct dynamic_odt single_S[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +000082 { /* cs0 */
83 FSL_DDR_ODT_NEVER,
84 FSL_DDR_ODT_ALL,
85 DDR3_RTT_40_OHM,
86 DDR3_RTT_OFF
87 },
88 {0, 0, 0, 0},
89 {0, 0, 0, 0},
90 {0, 0, 0, 0},
91};
92
York Sun454f5072011-08-26 11:32:43 -070093static const struct dynamic_odt dual_DD[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +000094 { /* cs0 */
95 FSL_DDR_ODT_NEVER,
96 FSL_DDR_ODT_SAME_DIMM,
97 DDR3_RTT_120_OHM,
98 DDR3_RTT_OFF
99 },
100 { /* cs1 */
101 FSL_DDR_ODT_OTHER_DIMM,
102 FSL_DDR_ODT_OTHER_DIMM,
103 DDR3_RTT_30_OHM,
104 DDR3_RTT_OFF
105 },
106 { /* cs2 */
107 FSL_DDR_ODT_NEVER,
108 FSL_DDR_ODT_SAME_DIMM,
109 DDR3_RTT_120_OHM,
110 DDR3_RTT_OFF
111 },
112 { /* cs3 */
113 FSL_DDR_ODT_OTHER_DIMM,
114 FSL_DDR_ODT_OTHER_DIMM,
115 DDR3_RTT_30_OHM,
116 DDR3_RTT_OFF
117 }
118};
119
York Sun454f5072011-08-26 11:32:43 -0700120static const struct dynamic_odt dual_DS[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000121 { /* cs0 */
122 FSL_DDR_ODT_NEVER,
123 FSL_DDR_ODT_SAME_DIMM,
124 DDR3_RTT_120_OHM,
125 DDR3_RTT_OFF
126 },
127 { /* cs1 */
128 FSL_DDR_ODT_OTHER_DIMM,
129 FSL_DDR_ODT_OTHER_DIMM,
130 DDR3_RTT_30_OHM,
131 DDR3_RTT_OFF
132 },
133 { /* cs2 */
134 FSL_DDR_ODT_OTHER_DIMM,
135 FSL_DDR_ODT_ALL,
136 DDR3_RTT_20_OHM,
137 DDR3_RTT_120_OHM
138 },
139 {0, 0, 0, 0}
140};
York Sun454f5072011-08-26 11:32:43 -0700141static const struct dynamic_odt dual_SD[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000142 { /* cs0 */
143 FSL_DDR_ODT_OTHER_DIMM,
144 FSL_DDR_ODT_ALL,
145 DDR3_RTT_20_OHM,
146 DDR3_RTT_120_OHM
147 },
148 {0, 0, 0, 0},
149 { /* cs2 */
150 FSL_DDR_ODT_NEVER,
151 FSL_DDR_ODT_SAME_DIMM,
152 DDR3_RTT_120_OHM,
153 DDR3_RTT_OFF
154 },
155 { /* cs3 */
156 FSL_DDR_ODT_OTHER_DIMM,
157 FSL_DDR_ODT_OTHER_DIMM,
158 DDR3_RTT_20_OHM,
159 DDR3_RTT_OFF
160 }
161};
162
York Sun454f5072011-08-26 11:32:43 -0700163static const struct dynamic_odt dual_SS[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000164 { /* cs0 */
165 FSL_DDR_ODT_OTHER_DIMM,
166 FSL_DDR_ODT_ALL,
167 DDR3_RTT_30_OHM,
168 DDR3_RTT_120_OHM
169 },
170 {0, 0, 0, 0},
171 { /* cs2 */
172 FSL_DDR_ODT_OTHER_DIMM,
173 FSL_DDR_ODT_ALL,
174 DDR3_RTT_30_OHM,
175 DDR3_RTT_120_OHM
176 },
177 {0, 0, 0, 0}
178};
179
York Sun454f5072011-08-26 11:32:43 -0700180static const struct dynamic_odt dual_D0[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000181 { /* cs0 */
182 FSL_DDR_ODT_NEVER,
183 FSL_DDR_ODT_SAME_DIMM,
184 DDR3_RTT_40_OHM,
185 DDR3_RTT_OFF
186 },
187 { /* cs1 */
188 FSL_DDR_ODT_NEVER,
189 FSL_DDR_ODT_NEVER,
190 DDR3_RTT_OFF,
191 DDR3_RTT_OFF
192 },
193 {0, 0, 0, 0},
194 {0, 0, 0, 0}
195};
196
York Sun454f5072011-08-26 11:32:43 -0700197static const struct dynamic_odt dual_0D[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000198 {0, 0, 0, 0},
199 {0, 0, 0, 0},
200 { /* cs2 */
201 FSL_DDR_ODT_NEVER,
202 FSL_DDR_ODT_SAME_DIMM,
203 DDR3_RTT_40_OHM,
204 DDR3_RTT_OFF
205 },
206 { /* cs3 */
207 FSL_DDR_ODT_NEVER,
208 FSL_DDR_ODT_NEVER,
209 DDR3_RTT_OFF,
210 DDR3_RTT_OFF
211 }
212};
213
York Sun454f5072011-08-26 11:32:43 -0700214static const struct dynamic_odt dual_S0[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000215 { /* cs0 */
216 FSL_DDR_ODT_NEVER,
217 FSL_DDR_ODT_CS,
218 DDR3_RTT_40_OHM,
219 DDR3_RTT_OFF
220 },
221 {0, 0, 0, 0},
222 {0, 0, 0, 0},
223 {0, 0, 0, 0}
224
225};
226
York Sun454f5072011-08-26 11:32:43 -0700227static const struct dynamic_odt dual_0S[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000228 {0, 0, 0, 0},
229 {0, 0, 0, 0},
230 { /* cs2 */
231 FSL_DDR_ODT_NEVER,
232 FSL_DDR_ODT_CS,
233 DDR3_RTT_40_OHM,
234 DDR3_RTT_OFF
235 },
236 {0, 0, 0, 0}
237
238};
239
York Sun454f5072011-08-26 11:32:43 -0700240static const struct dynamic_odt odt_unknown[4] = {
York Sunba0c2eb2011-01-10 12:03:00 +0000241 { /* cs0 */
242 FSL_DDR_ODT_NEVER,
243 FSL_DDR_ODT_CS,
244 DDR3_RTT_120_OHM,
245 DDR3_RTT_OFF
246 },
247 { /* cs1 */
248 FSL_DDR_ODT_NEVER,
249 FSL_DDR_ODT_CS,
250 DDR3_RTT_120_OHM,
251 DDR3_RTT_OFF
252 },
253 { /* cs2 */
254 FSL_DDR_ODT_NEVER,
255 FSL_DDR_ODT_CS,
256 DDR3_RTT_120_OHM,
257 DDR3_RTT_OFF
258 },
259 { /* cs3 */
260 FSL_DDR_ODT_NEVER,
261 FSL_DDR_ODT_CS,
262 DDR3_RTT_120_OHM,
263 DDR3_RTT_OFF
264 }
265};
York Sun454f5072011-08-26 11:32:43 -0700266#else /* CONFIG_FSL_DDR3 */
267static const struct dynamic_odt single_Q[4] = {
268 {0, 0, 0, 0},
269 {0, 0, 0, 0},
270 {0, 0, 0, 0},
271 {0, 0, 0, 0}
272};
273
274static const struct dynamic_odt single_D[4] = {
275 { /* cs0 */
276 FSL_DDR_ODT_NEVER,
277 FSL_DDR_ODT_ALL,
278 DDR2_RTT_150_OHM,
279 DDR2_RTT_OFF
280 },
281 { /* cs1 */
282 FSL_DDR_ODT_NEVER,
283 FSL_DDR_ODT_NEVER,
284 DDR2_RTT_OFF,
285 DDR2_RTT_OFF
286 },
287 {0, 0, 0, 0},
288 {0, 0, 0, 0}
289};
290
291static const struct dynamic_odt single_S[4] = {
292 { /* cs0 */
293 FSL_DDR_ODT_NEVER,
294 FSL_DDR_ODT_ALL,
295 DDR2_RTT_150_OHM,
296 DDR2_RTT_OFF
297 },
298 {0, 0, 0, 0},
299 {0, 0, 0, 0},
300 {0, 0, 0, 0},
301};
302
303static const struct dynamic_odt dual_DD[4] = {
304 { /* cs0 */
305 FSL_DDR_ODT_OTHER_DIMM,
306 FSL_DDR_ODT_OTHER_DIMM,
307 DDR2_RTT_75_OHM,
308 DDR2_RTT_OFF
309 },
310 { /* cs1 */
311 FSL_DDR_ODT_NEVER,
312 FSL_DDR_ODT_NEVER,
313 DDR2_RTT_OFF,
314 DDR2_RTT_OFF
315 },
316 { /* cs2 */
317 FSL_DDR_ODT_OTHER_DIMM,
318 FSL_DDR_ODT_OTHER_DIMM,
319 DDR2_RTT_75_OHM,
320 DDR2_RTT_OFF
321 },
322 { /* cs3 */
323 FSL_DDR_ODT_NEVER,
324 FSL_DDR_ODT_NEVER,
325 DDR2_RTT_OFF,
326 DDR2_RTT_OFF
327 }
328};
329
330static const struct dynamic_odt dual_DS[4] = {
331 { /* cs0 */
332 FSL_DDR_ODT_OTHER_DIMM,
333 FSL_DDR_ODT_OTHER_DIMM,
334 DDR2_RTT_75_OHM,
335 DDR2_RTT_OFF
336 },
337 { /* cs1 */
338 FSL_DDR_ODT_NEVER,
339 FSL_DDR_ODT_NEVER,
340 DDR2_RTT_OFF,
341 DDR2_RTT_OFF
342 },
343 { /* cs2 */
344 FSL_DDR_ODT_OTHER_DIMM,
345 FSL_DDR_ODT_OTHER_DIMM,
346 DDR2_RTT_75_OHM,
347 DDR2_RTT_OFF
348 },
349 {0, 0, 0, 0}
350};
351
352static const struct dynamic_odt dual_SD[4] = {
353 { /* cs0 */
354 FSL_DDR_ODT_OTHER_DIMM,
355 FSL_DDR_ODT_OTHER_DIMM,
356 DDR2_RTT_75_OHM,
357 DDR2_RTT_OFF
358 },
359 {0, 0, 0, 0},
360 { /* cs2 */
361 FSL_DDR_ODT_OTHER_DIMM,
362 FSL_DDR_ODT_OTHER_DIMM,
363 DDR2_RTT_75_OHM,
364 DDR2_RTT_OFF
365 },
366 { /* cs3 */
367 FSL_DDR_ODT_NEVER,
368 FSL_DDR_ODT_NEVER,
369 DDR2_RTT_OFF,
370 DDR2_RTT_OFF
371 }
372};
373
374static const struct dynamic_odt dual_SS[4] = {
375 { /* cs0 */
376 FSL_DDR_ODT_OTHER_DIMM,
377 FSL_DDR_ODT_OTHER_DIMM,
378 DDR2_RTT_75_OHM,
379 DDR2_RTT_OFF
380 },
381 {0, 0, 0, 0},
382 { /* cs2 */
383 FSL_DDR_ODT_OTHER_DIMM,
384 FSL_DDR_ODT_OTHER_DIMM,
385 DDR2_RTT_75_OHM,
386 DDR2_RTT_OFF
387 },
388 {0, 0, 0, 0}
389};
390
391static const struct dynamic_odt dual_D0[4] = {
392 { /* cs0 */
393 FSL_DDR_ODT_NEVER,
394 FSL_DDR_ODT_ALL,
395 DDR2_RTT_150_OHM,
396 DDR2_RTT_OFF
397 },
398 { /* cs1 */
399 FSL_DDR_ODT_NEVER,
400 FSL_DDR_ODT_NEVER,
401 DDR2_RTT_OFF,
402 DDR2_RTT_OFF
403 },
404 {0, 0, 0, 0},
405 {0, 0, 0, 0}
406};
407
408static const struct dynamic_odt dual_0D[4] = {
409 {0, 0, 0, 0},
410 {0, 0, 0, 0},
411 { /* cs2 */
412 FSL_DDR_ODT_NEVER,
413 FSL_DDR_ODT_ALL,
414 DDR2_RTT_150_OHM,
415 DDR2_RTT_OFF
416 },
417 { /* cs3 */
418 FSL_DDR_ODT_NEVER,
419 FSL_DDR_ODT_NEVER,
420 DDR2_RTT_OFF,
421 DDR2_RTT_OFF
422 }
423};
York Sunba0c2eb2011-01-10 12:03:00 +0000424
York Sun454f5072011-08-26 11:32:43 -0700425static const struct dynamic_odt dual_S0[4] = {
426 { /* cs0 */
427 FSL_DDR_ODT_NEVER,
428 FSL_DDR_ODT_CS,
429 DDR2_RTT_150_OHM,
430 DDR2_RTT_OFF
431 },
432 {0, 0, 0, 0},
433 {0, 0, 0, 0},
434 {0, 0, 0, 0}
435
436};
437
438static const struct dynamic_odt dual_0S[4] = {
439 {0, 0, 0, 0},
440 {0, 0, 0, 0},
441 { /* cs2 */
442 FSL_DDR_ODT_NEVER,
443 FSL_DDR_ODT_CS,
444 DDR2_RTT_150_OHM,
445 DDR2_RTT_OFF
446 },
447 {0, 0, 0, 0}
448
449};
450
451static const struct dynamic_odt odt_unknown[4] = {
452 { /* cs0 */
453 FSL_DDR_ODT_NEVER,
454 FSL_DDR_ODT_CS,
455 DDR2_RTT_75_OHM,
456 DDR2_RTT_OFF
457 },
458 { /* cs1 */
459 FSL_DDR_ODT_NEVER,
460 FSL_DDR_ODT_NEVER,
461 DDR2_RTT_OFF,
462 DDR2_RTT_OFF
463 },
464 { /* cs2 */
465 FSL_DDR_ODT_NEVER,
466 FSL_DDR_ODT_CS,
467 DDR2_RTT_75_OHM,
468 DDR2_RTT_OFF
469 },
470 { /* cs3 */
471 FSL_DDR_ODT_NEVER,
472 FSL_DDR_ODT_NEVER,
473 DDR2_RTT_OFF,
474 DDR2_RTT_OFF
475 }
476};
477#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500478unsigned int populate_memctl_options(int all_DIMMs_registered,
479 memctl_options_t *popts,
Haiying Wangfa440362008-10-03 12:36:55 -0400480 dimm_params_t *pdimm,
Kumar Gala124b0822008-08-26 15:01:29 -0500481 unsigned int ctrl_num)
482{
483 unsigned int i;
Kumar Gala72301602011-01-09 11:37:00 -0600484 char buffer[HWCONFIG_BUFFER_SIZE];
485 char *buf = NULL;
Kumar Gala59cb44c2011-11-09 10:05:21 -0600486#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
York Sun454f5072011-08-26 11:32:43 -0700487 const struct dynamic_odt *pdodt = odt_unknown;
Kumar Gala59cb44c2011-11-09 10:05:21 -0600488#endif
York Sunf0345e22011-08-24 09:40:26 -0700489 ulong ddr_freq;
Kumar Gala72301602011-01-09 11:37:00 -0600490
491 /*
492 * Extract hwconfig from environment since we have not properly setup
493 * the environment but need it for ddr config params
494 */
495 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
496 buf = buffer;
Kumar Gala124b0822008-08-26 15:01:29 -0500497
Kumar Gala59cb44c2011-11-09 10:05:21 -0600498#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
Kumar Gala124b0822008-08-26 15:01:29 -0500499 /* Chip select options. */
York Sunba0c2eb2011-01-10 12:03:00 +0000500 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
501 switch (pdimm[0].n_ranks) {
502 case 1:
503 pdodt = single_S;
504 break;
505 case 2:
506 pdodt = single_D;
507 break;
508 case 4:
509 pdodt = single_Q;
510 break;
511 }
512 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
513 switch (pdimm[0].n_ranks) {
514 case 2:
515 switch (pdimm[1].n_ranks) {
516 case 2:
517 pdodt = dual_DD;
518 break;
519 case 1:
520 pdodt = dual_DS;
521 break;
522 case 0:
523 pdodt = dual_D0;
524 break;
525 }
526 break;
527 case 1:
528 switch (pdimm[1].n_ranks) {
529 case 2:
530 pdodt = dual_SD;
531 break;
532 case 1:
533 pdodt = dual_SS;
534 break;
535 case 0:
536 pdodt = dual_S0;
537 break;
538 }
539 break;
540 case 0:
541 switch (pdimm[1].n_ranks) {
542 case 2:
543 pdodt = dual_0D;
544 break;
545 case 1:
546 pdodt = dual_0S;
547 break;
548 }
549 break;
550 }
551 }
Kumar Gala59cb44c2011-11-09 10:05:21 -0600552#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500553
554 /* Pick chip-select local options. */
555 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sun454f5072011-08-26 11:32:43 -0700556#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
York Sunba0c2eb2011-01-10 12:03:00 +0000557 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
558 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
559 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
560 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
561#else
562 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
563 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
564#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500565 popts->cs_local_opts[i].auto_precharge = 0;
566 }
567
568 /* Pick interleaving mode. */
569
570 /*
571 * 0 = no interleaving
572 * 1 = interleaving between 2 controllers
573 */
574 popts->memctl_interleaving = 0;
575
576 /*
577 * 0 = cacheline
578 * 1 = page
579 * 2 = (logical) bank
580 * 3 = superbank (only if CS interleaving is enabled)
581 */
582 popts->memctl_interleaving_mode = 0;
583
584 /*
585 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
586 * 1: page: bit to the left of the column bits selects the memctl
587 * 2: bank: bit to the left of the bank bits selects the memctl
588 * 3: superbank: bit to the left of the chip select selects the memctl
589 *
590 * NOTE: ba_intlv (rank interleaving) is independent of memory
591 * controller interleaving; it is only within a memory controller.
592 * Must use superbank interleaving if rank interleaving is used and
593 * memory controller interleaving is enabled.
594 */
595
596 /*
597 * 0 = no
598 * 0x40 = CS0,CS1
599 * 0x20 = CS2,CS3
600 * 0x60 = CS0,CS1 + CS2,CS3
601 * 0x04 = CS0,CS1,CS2,CS3
602 */
603 popts->ba_intlv_ctl = 0;
604
605 /* Memory Organization Parameters */
606 popts->registered_dimm_en = all_DIMMs_registered;
607
608 /* Operational Mode Paramters */
609
610 /* Pick ECC modes */
Kumar Gala124b0822008-08-26 15:01:29 -0500611 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
York Sun0ac71ea2011-01-10 12:02:57 +0000612#ifdef CONFIG_DDR_ECC
613 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
614 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
615 popts->ECC_mode = 1;
616 } else
617 popts->ECC_mode = 1;
Kumar Gala124b0822008-08-26 15:01:29 -0500618#endif
619 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
620
621 /*
622 * Choose DQS config
623 * 0 for DDR1
624 * 1 for DDR2
625 */
626#if defined(CONFIG_FSL_DDR1)
627 popts->DQS_config = 0;
Dave Liu4be87b22009-03-14 12:48:30 +0800628#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
Kumar Gala124b0822008-08-26 15:01:29 -0500629 popts->DQS_config = 1;
Kumar Gala124b0822008-08-26 15:01:29 -0500630#endif
631
632 /* Choose self-refresh during sleep. */
633 popts->self_refresh_in_sleep = 1;
634
635 /* Choose dynamic power management mode. */
636 popts->dynamic_power = 0;
637
York Sun5fb9f6f2011-05-27 07:25:48 +0800638 /*
639 * check first dimm for primary sdram width
640 * presuming all dimms are similar
641 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
642 */
York Sun3c5ffd42011-06-27 13:35:25 -0700643#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
644 if (pdimm[0].n_ranks != 0) {
645 if ((pdimm[0].data_width >= 64) && \
646 (pdimm[0].data_width <= 72))
647 popts->data_bus_width = 0;
648 else if ((pdimm[0].data_width >= 32) || \
649 (pdimm[0].data_width <= 40))
650 popts->data_bus_width = 1;
651 else {
652 panic("Error: data width %u is invalid!\n",
653 pdimm[0].data_width);
654 }
655 }
656#else
657 if (pdimm[0].n_ranks != 0) {
658 if (pdimm[0].primary_sdram_width == 64)
659 popts->data_bus_width = 0;
660 else if (pdimm[0].primary_sdram_width == 32)
661 popts->data_bus_width = 1;
662 else if (pdimm[0].primary_sdram_width == 16)
663 popts->data_bus_width = 2;
664 else {
665 panic("Error: primary sdram width %u is invalid!\n",
666 pdimm[0].primary_sdram_width);
667 }
668 }
669#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500670
671 /* Choose burst length. */
Dave Liu4be87b22009-03-14 12:48:30 +0800672#if defined(CONFIG_FSL_DDR3)
Dave Liu707aa5c2010-03-05 12:22:00 +0800673#if defined(CONFIG_E500MC)
674 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
675 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
676#else
York Sundd803dd2011-05-27 07:25:51 +0800677 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
678 /* 32-bit or 16-bit bus */
York Sun5fb9f6f2011-05-27 07:25:48 +0800679 popts->OTF_burst_chop_en = 0;
680 popts->burst_length = DDR_BL8;
681 } else {
682 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
683 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
684 }
Dave Liu707aa5c2010-03-05 12:22:00 +0800685#endif
Dave Liu4be87b22009-03-14 12:48:30 +0800686#else
687 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
688#endif
689
690 /* Choose ddr controller address mirror mode */
691#if defined(CONFIG_FSL_DDR3)
692 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
693#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500694
695 /* Global Timing Parameters. */
696 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
697
698 /* Pick a caslat override. */
699 popts->cas_latency_override = 0;
700 popts->cas_latency_override_value = 3;
701 if (popts->cas_latency_override) {
702 debug("using caslat override value = %u\n",
703 popts->cas_latency_override_value);
704 }
705
706 /* Decide whether to use the computed derated latency */
707 popts->use_derated_caslat = 0;
708
709 /* Choose an additive latency. */
710 popts->additive_latency_override = 0;
711 popts->additive_latency_override_value = 3;
712 if (popts->additive_latency_override) {
713 debug("using additive latency override value = %u\n",
714 popts->additive_latency_override_value);
715 }
716
717 /*
718 * 2T_EN setting
719 *
720 * Factors to consider for 2T_EN:
721 * - number of DIMMs installed
722 * - number of components, number of active ranks
723 * - how much time you want to spend playing around
724 */
Dave Liua06d74c2008-11-21 16:31:43 +0800725 popts->twoT_en = 0;
Kumar Gala124b0822008-08-26 15:01:29 -0500726 popts->threeT_en = 0;
727
York Sunba0c2eb2011-01-10 12:03:00 +0000728 /* for RDIMM, address parity enable */
729 popts->ap_en = 1;
730
Kumar Gala124b0822008-08-26 15:01:29 -0500731 /*
732 * BSTTOPRE precharge interval
733 *
734 * Set this to 0 for global auto precharge
735 *
736 * FIXME: Should this be configured in picoseconds?
737 * Why it should be in ps: better understanding of this
738 * relative to actual DRAM timing parameters such as tRAS.
739 * e.g. tRAS(min) = 40 ns
740 */
741 popts->bstopre = 0x100;
742
743 /* Minimum CKE pulse width -- tCKE(MIN) */
744 popts->tCKE_clock_pulse_width_ps
745 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
746
747 /*
748 * Window for four activates -- tFAW
749 *
750 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
751 * FIXME: varies depending upon number of column addresses or data
752 * FIXME: width, was considering looking at pdimm->primary_sdram_width
753 */
754#if defined(CONFIG_FSL_DDR1)
755 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
756
757#elif defined(CONFIG_FSL_DDR2)
758 /*
759 * x4/x8; some datasheets have 35000
760 * x16 wide columns only? Use 50000?
761 */
762 popts->tFAW_window_four_activates_ps = 37500;
763
764#elif defined(CONFIG_FSL_DDR3)
Dave Liu4be87b22009-03-14 12:48:30 +0800765 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
766#endif
767 popts->zq_en = 0;
768 popts->wrlvl_en = 0;
769#if defined(CONFIG_FSL_DDR3)
770 /*
771 * due to ddr3 dimm is fly-by topology
772 * we suggest to enable write leveling to
773 * meet the tQDSS under different loading.
774 */
775 popts->wrlvl_en = 1;
york1714e492010-07-02 22:25:56 +0000776 popts->zq_en = 1;
Dave Liu64ee7df2009-12-16 10:24:37 -0600777 popts->wrlvl_override = 0;
Kumar Gala124b0822008-08-26 15:01:29 -0500778#endif
779
Kumar Gala124b0822008-08-26 15:01:29 -0500780 /*
Haiying Wangb834f922008-10-03 12:37:10 -0400781 * Check interleaving configuration from environment.
782 * Please refer to doc/README.fsl-ddr for the detail.
Kumar Gala124b0822008-08-26 15:01:29 -0500783 *
784 * If memory controller interleaving is enabled, then the data
york93799ca2010-07-02 22:25:52 +0000785 * bus widths must be programmed identically for all memory controllers.
Haiying Wangb834f922008-10-03 12:37:10 -0400786 *
york93799ca2010-07-02 22:25:52 +0000787 * XXX: Attempt to set all controllers to the same chip select
Haiying Wangb834f922008-10-03 12:37:10 -0400788 * interleaving mode. It will do a best effort to get the
789 * requested ranks interleaved together such that the result
790 * should be a subset of the requested configuration.
Kumar Gala124b0822008-08-26 15:01:29 -0500791 */
Kumar Galac0f3b3c2009-02-06 09:56:34 -0600792#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
Kumar Gala72301602011-01-09 11:37:00 -0600793 if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
Haiying Wangb834f922008-10-03 12:37:10 -0400794 if (pdimm[0].n_ranks == 0) {
york93799ca2010-07-02 22:25:52 +0000795 printf("There is no rank on CS0 for controller %d. Because only"
796 " rank on CS0 and ranks chip-select interleaved with CS0"
Ed Swarthoutb135d932008-10-29 09:21:44 -0500797 " are controller interleaved, force non memory "
york93799ca2010-07-02 22:25:52 +0000798 "controller interleaving\n", ctrl_num);
Haiying Wangb834f922008-10-03 12:37:10 -0400799 popts->memctl_interleaving = 0;
800 } else {
801 popts->memctl_interleaving = 1;
york93799ca2010-07-02 22:25:52 +0000802 /*
803 * test null first. if CONFIG_HWCONFIG is not defined
804 * hwconfig_arg_cmp returns non-zero
805 */
Kumar Gala72301602011-01-09 11:37:00 -0600806 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
807 "null", buf)) {
Kumar Gala64042092010-07-14 10:04:21 -0500808 popts->memctl_interleaving = 0;
809 debug("memory controller interleaving disabled.\n");
Kumar Gala72301602011-01-09 11:37:00 -0600810 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
811 "ctlr_intlv",
812 "cacheline", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400813 popts->memctl_interleaving_mode =
814 FSL_DDR_CACHE_LINE_INTERLEAVING;
Kumar Gala72301602011-01-09 11:37:00 -0600815 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
816 "page", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400817 popts->memctl_interleaving_mode =
818 FSL_DDR_PAGE_INTERLEAVING;
Kumar Gala72301602011-01-09 11:37:00 -0600819 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
820 "bank", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400821 popts->memctl_interleaving_mode =
822 FSL_DDR_BANK_INTERLEAVING;
Kumar Gala72301602011-01-09 11:37:00 -0600823 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
824 "superbank", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400825 popts->memctl_interleaving_mode =
826 FSL_DDR_SUPERBANK_INTERLEAVING;
Kumar Gala64042092010-07-14 10:04:21 -0500827 else {
828 popts->memctl_interleaving = 0;
829 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
830 }
Haiying Wangb834f922008-10-03 12:37:10 -0400831 }
832 }
Dave Liu0f9318f2009-11-12 07:26:37 +0800833#endif
Kumar Gala72301602011-01-09 11:37:00 -0600834 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
Dave Liu0f9318f2009-11-12 07:26:37 +0800835 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
Kumar Gala64042092010-07-14 10:04:21 -0500836 /* test null first. if CONFIG_HWCONFIG is not defined,
Kumar Gala72301602011-01-09 11:37:00 -0600837 * hwconfig_subarg_cmp_f returns non-zero */
838 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
839 "null", buf))
york93799ca2010-07-02 22:25:52 +0000840 debug("bank interleaving disabled.\n");
Kumar Gala72301602011-01-09 11:37:00 -0600841 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
842 "cs0_cs1", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400843 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
Kumar Gala72301602011-01-09 11:37:00 -0600844 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
845 "cs2_cs3", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400846 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
Kumar Gala72301602011-01-09 11:37:00 -0600847 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
848 "cs0_cs1_and_cs2_cs3", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400849 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
Kumar Gala72301602011-01-09 11:37:00 -0600850 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
851 "cs0_cs1_cs2_cs3", buf))
Haiying Wangb834f922008-10-03 12:37:10 -0400852 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
853 else
york93799ca2010-07-02 22:25:52 +0000854 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
Haiying Wangb834f922008-10-03 12:37:10 -0400855 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
856 case FSL_DDR_CS0_CS1_CS2_CS3:
york93799ca2010-07-02 22:25:52 +0000857#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
yorkf4f93c62010-07-02 22:25:53 +0000858 if (pdimm[0].n_ranks < 4) {
york93799ca2010-07-02 22:25:52 +0000859 popts->ba_intlv_ctl = 0;
860 printf("Not enough bank(chip-select) for "
861 "CS0+CS1+CS2+CS3 on controller %d, "
862 "force non-interleaving!\n", ctrl_num);
863 }
864#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
yorkf4f93c62010-07-02 22:25:53 +0000865 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
york93799ca2010-07-02 22:25:52 +0000866 popts->ba_intlv_ctl = 0;
867 printf("Not enough bank(chip-select) for "
868 "CS0+CS1+CS2+CS3 on controller %d, "
869 "force non-interleaving!\n", ctrl_num);
870 }
871 if (pdimm[0].capacity != pdimm[1].capacity) {
872 popts->ba_intlv_ctl = 0;
873 printf("Not identical DIMM size for "
874 "CS0+CS1+CS2+CS3 on controller %d, "
875 "force non-interleaving!\n", ctrl_num);
876 }
877#endif
878 break;
Haiying Wangb834f922008-10-03 12:37:10 -0400879 case FSL_DDR_CS0_CS1:
yorkf4f93c62010-07-02 22:25:53 +0000880 if (pdimm[0].n_ranks < 2) {
Haiying Wangb834f922008-10-03 12:37:10 -0400881 popts->ba_intlv_ctl = 0;
Ed Swarthoutb135d932008-10-29 09:21:44 -0500882 printf("Not enough bank(chip-select) for "
york93799ca2010-07-02 22:25:52 +0000883 "CS0+CS1 on controller %d, "
884 "force non-interleaving!\n", ctrl_num);
Haiying Wangb834f922008-10-03 12:37:10 -0400885 }
886 break;
887 case FSL_DDR_CS2_CS3:
york93799ca2010-07-02 22:25:52 +0000888#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
yorkf4f93c62010-07-02 22:25:53 +0000889 if (pdimm[0].n_ranks < 4) {
Haiying Wangb834f922008-10-03 12:37:10 -0400890 popts->ba_intlv_ctl = 0;
york93799ca2010-07-02 22:25:52 +0000891 printf("Not enough bank(chip-select) for CS2+CS3 "
892 "on controller %d, force non-interleaving!\n", ctrl_num);
Haiying Wangb834f922008-10-03 12:37:10 -0400893 }
york93799ca2010-07-02 22:25:52 +0000894#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
yorkf4f93c62010-07-02 22:25:53 +0000895 if (pdimm[1].n_ranks < 2) {
york93799ca2010-07-02 22:25:52 +0000896 popts->ba_intlv_ctl = 0;
897 printf("Not enough bank(chip-select) for CS2+CS3 "
898 "on controller %d, force non-interleaving!\n", ctrl_num);
899 }
900#endif
Haiying Wangb834f922008-10-03 12:37:10 -0400901 break;
902 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
york93799ca2010-07-02 22:25:52 +0000903#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
yorkf4f93c62010-07-02 22:25:53 +0000904 if (pdimm[0].n_ranks < 4) {
york93799ca2010-07-02 22:25:52 +0000905 popts->ba_intlv_ctl = 0;
906 printf("Not enough bank(CS) for CS0+CS1 and "
907 "CS2+CS3 on controller %d, "
908 "force non-interleaving!\n", ctrl_num);
909 }
910#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
yorkf4f93c62010-07-02 22:25:53 +0000911 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
Haiying Wangb834f922008-10-03 12:37:10 -0400912 popts->ba_intlv_ctl = 0;
york93799ca2010-07-02 22:25:52 +0000913 printf("Not enough bank(CS) for CS0+CS1 and "
914 "CS2+CS3 on controller %d, "
915 "force non-interleaving!\n", ctrl_num);
Haiying Wangb834f922008-10-03 12:37:10 -0400916 }
york93799ca2010-07-02 22:25:52 +0000917#endif
Haiying Wangb834f922008-10-03 12:37:10 -0400918 break;
919 default:
920 popts->ba_intlv_ctl = 0;
921 break;
922 }
923 }
Kumar Gala124b0822008-08-26 15:01:29 -0500924
Kumar Gala72301602011-01-09 11:37:00 -0600925 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
926 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
york42603722010-07-02 22:25:54 +0000927 popts->addr_hash = 0;
Kumar Gala72301602011-01-09 11:37:00 -0600928 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
929 "true", buf))
york42603722010-07-02 22:25:54 +0000930 popts->addr_hash = 1;
931 }
932
yorkf4f93c62010-07-02 22:25:53 +0000933 if (pdimm[0].n_ranks == 4)
934 popts->quad_rank_present = 1;
935
York Sunf0345e22011-08-24 09:40:26 -0700936 ddr_freq = get_ddr_freq(0) / 1000000;
937 if (popts->registered_dimm_en) {
938 popts->rcw_override = 1;
939 popts->rcw_1 = 0x000a5a00;
940 if (ddr_freq <= 800)
941 popts->rcw_2 = 0x00000000;
942 else if (ddr_freq <= 1066)
943 popts->rcw_2 = 0x00100000;
944 else if (ddr_freq <= 1333)
945 popts->rcw_2 = 0x00200000;
946 else
947 popts->rcw_2 = 0x00300000;
948 }
949
Haiying Wangfa440362008-10-03 12:36:55 -0400950 fsl_ddr_board_options(popts, pdimm, ctrl_num);
Kumar Gala124b0822008-08-26 15:01:29 -0500951
952 return 0;
953}
york93799ca2010-07-02 22:25:52 +0000954
955void check_interleaving_options(fsl_ddr_info_t *pinfo)
956{
957 int i, j, check_n_ranks, intlv_fixed = 0;
958 unsigned long long check_rank_density;
959 /*
960 * Check if all controllers are configured for memory
961 * controller interleaving. Identical dimms are recommended. At least
962 * the size should be checked.
963 */
964 j = 0;
965 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
966 check_rank_density = pinfo->dimm_params[0][0].rank_density;
967 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
968 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
969 (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
970 (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
971 j++;
972 }
973 }
974 if (j != CONFIG_NUM_DDR_CONTROLLERS) {
975 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
976 if (pinfo->memctl_opts[i].memctl_interleaving) {
977 pinfo->memctl_opts[i].memctl_interleaving = 0;
978 intlv_fixed = 1;
979 }
980 if (intlv_fixed)
981 printf("Not all DIMMs are identical in size. "
982 "Memory controller interleaving disabled.\n");
983 }
984}
Kumar Galaf582d982011-01-09 14:06:28 -0600985
986int fsl_use_spd(void)
987{
988 int use_spd = 0;
989
990#ifdef CONFIG_DDR_SPD
Kumar Gala72301602011-01-09 11:37:00 -0600991 char buffer[HWCONFIG_BUFFER_SIZE];
992 char *buf = NULL;
993
994 /*
995 * Extract hwconfig from environment since we have not properly setup
996 * the environment but need it for ddr config params
997 */
998 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
999 buf = buffer;
1000
Kumar Galaf582d982011-01-09 14:06:28 -06001001 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
Kumar Gala72301602011-01-09 11:37:00 -06001002 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1003 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
Kumar Galaf582d982011-01-09 14:06:28 -06001004 use_spd = 1;
Kumar Gala72301602011-01-09 11:37:00 -06001005 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
1006 "fixed", buf))
Kumar Galaf582d982011-01-09 14:06:28 -06001007 use_spd = 0;
1008 else
1009 use_spd = 1;
1010 } else
1011 use_spd = 1;
1012#endif
1013
1014 return use_spd;
1015}