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git01.mediatek.com / filogic / uboot / f6e6e1acae1ea1870e52d73c8ef35840bb03ce0a / . / configs / at91sam9rlek_dataflash_defconfig
blob: 6c2547006f77a5b92b3b6d33f1a8fd87bcc9c658 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_ARM=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]2CONFIG_ARCH_CPU_INIT=y
Masahiro Yamadaaf908ee2015-02-20 17:04:01 +0900[diff] [blame]3CONFIG_ARCH_AT91=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x21F00000
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]5CONFIG_TARGET_AT91SAM9RLEK=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]6CONFIG_SYS_MALLOC_F_LEN=0x2000
Markus Klotzbuecher7bd60e62019-05-15 15:15:54 +0200[diff] [blame]7CONFIG_ENV_SIZE=0x4200
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame^]8CONFIG_ENV_SECT_SIZE=0x210
Markus Klotzbuecher7bd60e62019-05-15 15:15:54 +0200[diff] [blame]9CONFIG_ENV_OFFSET=0x4200
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame^]10CONFIG_DM_GPIO=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]11CONFIG_NR_DRAM_BANKS=1
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]12CONFIG_DEBUG_UART_BOARD_INIT=y
13CONFIG_DEBUG_UART_BASE=0xfffff200
14CONFIG_DEBUG_UART_CLOCK=100000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]15CONFIG_DEBUG_UART=y
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]16CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]17CONFIG_BOOTDELAY=3
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]18CONFIG_USE_BOOTARGS=y
19CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]20# CONFIG_CONSOLE_MUX is not set
21CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]22# CONFIG_DISPLAY_BOARDINFO is not set
Wu, Josha9b5d1a2015-02-03 18:19:05 +0800[diff] [blame]23CONFIG_HUSH_PARSER=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]24CONFIG_SYS_PROMPT="U-Boot> "
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]25# CONFIG_CMD_BDI is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]26CONFIG_CMD_BOOTZ=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]27# CONFIG_CMD_IMI is not set
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]28# CONFIG_CMD_LOADS is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]29CONFIG_CMD_MMC=y
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]30CONFIG_CMD_NAND=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]31# CONFIG_CMD_SOURCE is not set
32# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]33CONFIG_CMD_FAT=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]34CONFIG_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]35CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]36CONFIG_ENV_IS_IN_SPI_FLASH=y
Patrick Delaunayf8e932e2019-02-27 15:20:38 +0100[diff] [blame]37CONFIG_USE_ENV_SPI_MAX_HZ=y
38CONFIG_ENV_SPI_MAX_HZ=15000000
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]39CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Michal Simek2f785a12018-02-26 16:01:02 +0100[diff] [blame]40# CONFIG_NET is not set
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]41CONFIG_DM=y
42CONFIG_CLK=y
43CONFIG_CLK_AT91=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]44CONFIG_AT91_GPIO=y
45CONFIG_DM_MMC=y
46CONFIG_GENERIC_ATMEL_MCI=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]47CONFIG_MTD=y
Miquel Raynald0935362019-10-03 19:50:03 +0200[diff] [blame]48CONFIG_MTD_RAW_NAND=y
Stefan Roese23b37f92019-08-22 12:28:04 +0200[diff] [blame]49# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
Adam Ford9c519182018-07-08 08:11:07 -0500[diff] [blame]50CONFIG_NAND_ATMEL=y
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]51CONFIG_DM_SPI_FLASH=y
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]52CONFIG_SPI_FLASH_ATMEL=y
53CONFIG_SPI_FLASH_DATAFLASH=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]54CONFIG_PINCTRL=y
55CONFIG_PINCTRL_AT91=y
56CONFIG_DM_SERIAL=y
Wenyou Yangde5793e2017-04-18 15:28:29 +0800[diff] [blame]57CONFIG_DEBUG_UART_ATMEL=y
Wenyou Yangde5793e2017-04-18 15:28:29 +0800[diff] [blame]58CONFIG_DEBUG_UART_ANNOUNCE=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]59CONFIG_ATMEL_USART=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]60CONFIG_SPI=y
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]61CONFIG_DM_SPI=y
Wenyou.Yang@microchip.com272167d2017-08-15 17:40:27 +0800[diff] [blame]62CONFIG_TIMER=y
63CONFIG_ATMEL_PIT_TIMER=y
Simon Glass169bb3b2016-10-17 20:12:56 -0600[diff] [blame]64CONFIG_LCD=y