Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2011 The Chromium OS Authors. |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
Allen Martin | 55d98a1 | 2012-08-31 08:30:00 +0000 | [diff] [blame] | 6 | /* Tegra20 high-level function multiplexing */ |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 7 | #include <log.h> |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 8 | #include <asm/arch/clock.h> |
Simon Glass | 43b1a7c | 2012-01-11 12:42:23 +0000 | [diff] [blame] | 9 | #include <asm/arch/funcmux.h> |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 10 | #include <asm/arch/pinmux.h> |
| 11 | |
Simon Glass | 11ecb38 | 2012-10-17 13:24:46 +0000 | [diff] [blame] | 12 | /* |
| 13 | * The PINMUX macro is used to set up pinmux tables. |
| 14 | */ |
| 15 | #define PINMUX(grp, mux, pupd, tri) \ |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 16 | {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri} |
Simon Glass | 11ecb38 | 2012-10-17 13:24:46 +0000 | [diff] [blame] | 17 | |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 18 | static const struct pmux_pingrp_config disp1_default[] = { |
Simon Glass | 11ecb38 | 2012-10-17 13:24:46 +0000 | [diff] [blame] | 19 | PINMUX(LDI, DISPA, NORMAL, NORMAL), |
| 20 | PINMUX(LHP0, DISPA, NORMAL, NORMAL), |
| 21 | PINMUX(LHP1, DISPA, NORMAL, NORMAL), |
| 22 | PINMUX(LHP2, DISPA, NORMAL, NORMAL), |
| 23 | PINMUX(LHS, DISPA, NORMAL, NORMAL), |
| 24 | PINMUX(LM0, RSVD4, NORMAL, NORMAL), |
| 25 | PINMUX(LPP, DISPA, NORMAL, NORMAL), |
| 26 | PINMUX(LPW0, DISPA, NORMAL, NORMAL), |
| 27 | PINMUX(LPW2, DISPA, NORMAL, NORMAL), |
| 28 | PINMUX(LSC0, DISPA, NORMAL, NORMAL), |
| 29 | PINMUX(LSPI, DISPA, NORMAL, NORMAL), |
| 30 | PINMUX(LVP1, DISPA, NORMAL, NORMAL), |
| 31 | PINMUX(LVS, DISPA, NORMAL, NORMAL), |
| 32 | PINMUX(SLXD, SPDIF, NORMAL, NORMAL), |
| 33 | }; |
| 34 | |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 35 | int funcmux_select(enum periph_id id, int config) |
| 36 | { |
Simon Glass | 43b1a7c | 2012-01-11 12:42:23 +0000 | [diff] [blame] | 37 | int bad_config = config != FUNCMUX_DEFAULT; |
Simon Glass | 3ba99a3 | 2012-01-11 12:42:22 +0000 | [diff] [blame] | 38 | |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 39 | switch (id) { |
| 40 | case PERIPH_ID_UART1: |
Stephen Warren | 59f9010 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 41 | switch (config) { |
| 42 | case FUNCMUX_UART1_IRRX_IRTX: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 43 | pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA); |
| 44 | pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA); |
| 45 | pinmux_tristate_disable(PMUX_PINGRP_IRRX); |
| 46 | pinmux_tristate_disable(PMUX_PINGRP_IRTX); |
Stephen Warren | 59f9010 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 47 | break; |
| 48 | case FUNCMUX_UART1_UAA_UAB: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 49 | pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA); |
| 50 | pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA); |
| 51 | pinmux_tristate_disable(PMUX_PINGRP_UAA); |
| 52 | pinmux_tristate_disable(PMUX_PINGRP_UAB); |
Stephen Warren | 59f9010 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 53 | bad_config = 0; |
| 54 | break; |
Stephen Warren | e4c01a8 | 2012-05-16 05:59:59 +0000 | [diff] [blame] | 55 | case FUNCMUX_UART1_GPU: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 56 | pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA); |
| 57 | pinmux_tristate_disable(PMUX_PINGRP_GPU); |
Stephen Warren | e4c01a8 | 2012-05-16 05:59:59 +0000 | [diff] [blame] | 58 | bad_config = 0; |
| 59 | break; |
Lucas Stach | 4de6eec | 2012-05-16 08:21:02 +0000 | [diff] [blame] | 60 | case FUNCMUX_UART1_SDIO1: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 61 | pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA); |
| 62 | pinmux_tristate_disable(PMUX_PINGRP_SDIO1); |
Lucas Stach | 4de6eec | 2012-05-16 08:21:02 +0000 | [diff] [blame] | 63 | bad_config = 0; |
| 64 | break; |
Stephen Warren | 59f9010 | 2012-05-14 13:13:45 +0000 | [diff] [blame] | 65 | } |
| 66 | if (!bad_config) { |
Simon Glass | 3ba99a3 | 2012-01-11 12:42:22 +0000 | [diff] [blame] | 67 | /* |
| 68 | * Tegra appears to boot with function UARTA pre- |
| 69 | * selected on mux group SDB. If two mux groups are |
| 70 | * both set to the same function, it's unclear which |
| 71 | * group's pins drive the RX signals into the HW. |
| 72 | * For UARTA, SDB certainly overrides group IRTX in |
| 73 | * practice. To solve this, configure some alternative |
| 74 | * function on SDB to avoid the conflict. Also, tri- |
| 75 | * state the group to avoid driving any signal onto it |
| 76 | * until we know what's connected. |
| 77 | */ |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 78 | pinmux_tristate_enable(PMUX_PINGRP_SDB); |
| 79 | pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); |
Simon Glass | 3ba99a3 | 2012-01-11 12:42:22 +0000 | [diff] [blame] | 80 | } |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 81 | break; |
| 82 | |
| 83 | case PERIPH_ID_UART2: |
Stephen Warren | 811af73 | 2013-01-22 06:20:08 +0000 | [diff] [blame] | 84 | if (config == FUNCMUX_UART2_UAD) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 85 | pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB); |
| 86 | pinmux_tristate_disable(PMUX_PINGRP_UAD); |
Simon Glass | 3ba99a3 | 2012-01-11 12:42:22 +0000 | [diff] [blame] | 87 | } |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 88 | break; |
| 89 | |
| 90 | case PERIPH_ID_UART4: |
Simon Glass | 43b1a7c | 2012-01-11 12:42:23 +0000 | [diff] [blame] | 91 | if (config == FUNCMUX_UART4_GMC) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 92 | pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD); |
| 93 | pinmux_tristate_disable(PMUX_PINGRP_GMC); |
Simon Glass | 3ba99a3 | 2012-01-11 12:42:22 +0000 | [diff] [blame] | 94 | } |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 95 | break; |
| 96 | |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 97 | case PERIPH_ID_DVC_I2C: |
| 98 | /* there is only one selection, pinmux_config is ignored */ |
| 99 | if (config == FUNCMUX_DVC_I2CP) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 100 | pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C); |
| 101 | pinmux_tristate_disable(PMUX_PINGRP_I2CP); |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 102 | } |
| 103 | break; |
| 104 | |
| 105 | case PERIPH_ID_I2C1: |
| 106 | /* support pinmux_config of 0 for now, */ |
| 107 | if (config == FUNCMUX_I2C1_RM) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 108 | pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C); |
| 109 | pinmux_tristate_disable(PMUX_PINGRP_RM); |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 110 | } |
| 111 | break; |
| 112 | case PERIPH_ID_I2C2: /* I2C2 */ |
| 113 | switch (config) { |
| 114 | case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */ |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 115 | pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2); |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 116 | /* PTA to HDMI */ |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 117 | pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI); |
| 118 | pinmux_tristate_disable(PMUX_PINGRP_DDC); |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 119 | break; |
| 120 | case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */ |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 121 | pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2); |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 122 | /* set DDC_SEL to RSVDx (RSVD2 works for now) */ |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 123 | pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2); |
| 124 | pinmux_tristate_disable(PMUX_PINGRP_PTA); |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 125 | bad_config = 0; |
| 126 | break; |
| 127 | } |
| 128 | break; |
| 129 | case PERIPH_ID_I2C3: /* I2C3 */ |
| 130 | /* support pinmux_config of 0 for now */ |
| 131 | if (config == FUNCMUX_I2C3_DTF) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 132 | pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3); |
| 133 | pinmux_tristate_disable(PMUX_PINGRP_DTF); |
Simon Glass | d8c03b8 | 2012-01-11 12:42:24 +0000 | [diff] [blame] | 134 | } |
| 135 | break; |
| 136 | |
Stephen Warren | b6d1901 | 2012-05-16 13:54:06 +0000 | [diff] [blame] | 137 | case PERIPH_ID_SDMMC1: |
| 138 | if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 139 | pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); |
| 140 | pinmux_tristate_disable(PMUX_PINGRP_SDIO1); |
Stephen Warren | b6d1901 | 2012-05-16 13:54:06 +0000 | [diff] [blame] | 141 | } |
| 142 | break; |
| 143 | |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 144 | case PERIPH_ID_SDMMC2: |
| 145 | if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 146 | pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2); |
| 147 | pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 148 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 149 | pinmux_tristate_disable(PMUX_PINGRP_DTA); |
| 150 | pinmux_tristate_disable(PMUX_PINGRP_DTD); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 151 | } |
| 152 | break; |
| 153 | |
| 154 | case PERIPH_ID_SDMMC3: |
| 155 | switch (config) { |
| 156 | case FUNCMUX_SDMMC3_SDB_SLXA_8BIT: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 157 | pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3); |
| 158 | pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3); |
| 159 | pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3); |
| 160 | pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 161 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 162 | pinmux_tristate_disable(PMUX_PINGRP_SLXA); |
| 163 | pinmux_tristate_disable(PMUX_PINGRP_SLXC); |
| 164 | pinmux_tristate_disable(PMUX_PINGRP_SLXD); |
| 165 | pinmux_tristate_disable(PMUX_PINGRP_SLXK); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 166 | /* fall through */ |
| 167 | |
| 168 | case FUNCMUX_SDMMC3_SDB_4BIT: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 169 | pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); |
| 170 | pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3); |
| 171 | pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 172 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 173 | pinmux_tristate_disable(PMUX_PINGRP_SDB); |
| 174 | pinmux_tristate_disable(PMUX_PINGRP_SDC); |
| 175 | pinmux_tristate_disable(PMUX_PINGRP_SDD); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 176 | bad_config = 0; |
| 177 | break; |
| 178 | } |
| 179 | break; |
| 180 | |
| 181 | case PERIPH_ID_SDMMC4: |
| 182 | switch (config) { |
| 183 | case FUNCMUX_SDMMC4_ATC_ATD_8BIT: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 184 | pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4); |
| 185 | pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 186 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 187 | pinmux_tristate_disable(PMUX_PINGRP_ATC); |
| 188 | pinmux_tristate_disable(PMUX_PINGRP_ATD); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 189 | break; |
| 190 | |
| 191 | case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 192 | pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); |
| 193 | pinmux_tristate_disable(PMUX_PINGRP_GME); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 194 | /* fall through */ |
| 195 | |
| 196 | case FUNCMUX_SDMMC4_ATB_GMA_4_BIT: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 197 | pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); |
| 198 | pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 199 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 200 | pinmux_tristate_disable(PMUX_PINGRP_ATB); |
| 201 | pinmux_tristate_disable(PMUX_PINGRP_GMA); |
Simon Glass | fb1ea63 | 2012-01-11 12:42:25 +0000 | [diff] [blame] | 202 | bad_config = 0; |
| 203 | break; |
| 204 | } |
| 205 | break; |
| 206 | |
Simon Glass | 5dc0461 | 2012-04-17 09:01:32 +0000 | [diff] [blame] | 207 | case PERIPH_ID_KBC: |
| 208 | if (config == FUNCMUX_DEFAULT) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 209 | enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA, |
| 210 | PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC, |
| 211 | PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE, |
| 212 | PMUX_PINGRP_KBCF}; |
Simon Glass | 5dc0461 | 2012-04-17 09:01:32 +0000 | [diff] [blame] | 213 | int i; |
| 214 | |
| 215 | for (i = 0; i < ARRAY_SIZE(grp); i++) { |
| 216 | pinmux_tristate_disable(grp[i]); |
| 217 | pinmux_set_func(grp[i], PMUX_FUNC_KBC); |
| 218 | pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); |
| 219 | } |
Lucas Stach | 53c7911 | 2012-05-31 01:51:01 +0000 | [diff] [blame] | 220 | } |
| 221 | break; |
| 222 | |
| 223 | case PERIPH_ID_USB2: |
| 224 | if (config == FUNCMUX_USB2_ULPI) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 225 | pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI); |
| 226 | pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI); |
| 227 | pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI); |
Simon Glass | 5dc0461 | 2012-04-17 09:01:32 +0000 | [diff] [blame] | 228 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 229 | pinmux_tristate_disable(PMUX_PINGRP_UAA); |
| 230 | pinmux_tristate_disable(PMUX_PINGRP_UAB); |
| 231 | pinmux_tristate_disable(PMUX_PINGRP_UDA); |
Simon Glass | 5dc0461 | 2012-04-17 09:01:32 +0000 | [diff] [blame] | 232 | } |
Lucas Stach | 53c7911 | 2012-05-31 01:51:01 +0000 | [diff] [blame] | 233 | break; |
Simon Glass | 5dc0461 | 2012-04-17 09:01:32 +0000 | [diff] [blame] | 234 | |
Stephen Warren | 1bdbc9f | 2012-06-12 08:33:39 +0000 | [diff] [blame] | 235 | case PERIPH_ID_SPI1: |
| 236 | if (config == FUNCMUX_SPI1_GMC_GMD) { |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 237 | pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); |
| 238 | pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); |
Stephen Warren | 1bdbc9f | 2012-06-12 08:33:39 +0000 | [diff] [blame] | 239 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 240 | pinmux_tristate_disable(PMUX_PINGRP_GMC); |
| 241 | pinmux_tristate_disable(PMUX_PINGRP_GMD); |
Stephen Warren | 1bdbc9f | 2012-06-12 08:33:39 +0000 | [diff] [blame] | 242 | } |
| 243 | break; |
| 244 | |
Simon Glass | fdf5473 | 2012-07-29 20:53:26 +0000 | [diff] [blame] | 245 | case PERIPH_ID_NDFLASH: |
Lucas Stach | 93748d3 | 2012-09-27 13:04:27 +0000 | [diff] [blame] | 246 | switch (config) { |
| 247 | case FUNCMUX_NDFLASH_ATC: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 248 | pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND); |
| 249 | pinmux_tristate_disable(PMUX_PINGRP_ATC); |
Lucas Stach | 93748d3 | 2012-09-27 13:04:27 +0000 | [diff] [blame] | 250 | break; |
| 251 | case FUNCMUX_NDFLASH_KBC_8_BIT: |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 252 | pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); |
Lucas Stach | c9109a1 | 2015-03-27 01:31:44 +0100 | [diff] [blame] | 253 | pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 254 | pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); |
| 255 | pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); |
| 256 | pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); |
| 257 | pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); |
Lucas Stach | 93748d3 | 2012-09-27 13:04:27 +0000 | [diff] [blame] | 258 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 259 | pinmux_tristate_disable(PMUX_PINGRP_KBCA); |
Lucas Stach | c9109a1 | 2015-03-27 01:31:44 +0100 | [diff] [blame] | 260 | pinmux_tristate_disable(PMUX_PINGRP_KBCB); |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 261 | pinmux_tristate_disable(PMUX_PINGRP_KBCC); |
| 262 | pinmux_tristate_disable(PMUX_PINGRP_KBCD); |
| 263 | pinmux_tristate_disable(PMUX_PINGRP_KBCE); |
| 264 | pinmux_tristate_disable(PMUX_PINGRP_KBCF); |
Lucas Stach | 93748d3 | 2012-09-27 13:04:27 +0000 | [diff] [blame] | 265 | |
| 266 | bad_config = 0; |
| 267 | break; |
Simon Glass | fdf5473 | 2012-07-29 20:53:26 +0000 | [diff] [blame] | 268 | } |
| 269 | break; |
Simon Glass | 11ecb38 | 2012-10-17 13:24:46 +0000 | [diff] [blame] | 270 | case PERIPH_ID_DISP1: |
| 271 | if (config == FUNCMUX_DEFAULT) { |
| 272 | int i; |
| 273 | |
Stephen Warren | f27f4e8 | 2014-03-21 12:28:58 -0600 | [diff] [blame] | 274 | for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) { |
Simon Glass | 11ecb38 | 2012-10-17 13:24:46 +0000 | [diff] [blame] | 275 | pinmux_set_func(i, PMUX_FUNC_DISPA); |
| 276 | pinmux_tristate_disable(i); |
| 277 | pinmux_set_pullupdown(i, PMUX_PULL_NORMAL); |
| 278 | } |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 279 | pinmux_config_pingrp_table(disp1_default, |
| 280 | ARRAY_SIZE(disp1_default)); |
Simon Glass | 11ecb38 | 2012-10-17 13:24:46 +0000 | [diff] [blame] | 281 | } |
| 282 | break; |
Simon Glass | fdf5473 | 2012-07-29 20:53:26 +0000 | [diff] [blame] | 283 | |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 284 | default: |
| 285 | debug("%s: invalid periph_id %d", __func__, id); |
| 286 | return -1; |
| 287 | } |
| 288 | |
Simon Glass | 3ba99a3 | 2012-01-11 12:42:22 +0000 | [diff] [blame] | 289 | if (bad_config) { |
| 290 | debug("%s: invalid config %d for periph_id %d", __func__, |
| 291 | config, id); |
| 292 | return -1; |
| 293 | } |
| 294 | |
Simon Glass | 84a97c5 | 2011-11-28 15:04:38 +0000 | [diff] [blame] | 295 | return 0; |
| 296 | } |