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Marek Vasut78414832019-03-04 21:38:10 +01001// SPDX-License-Identifier: GPL-2.0
Marek Vasut4eb4e6e2018-01-08 14:01:40 +01002/*
Marek Vasutfd440592023-01-26 21:01:51 +01003 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
4 * Reset
Marek Vasut4eb4e6e2018-01-08 14:01:40 +01005 *
Marek Vasutfd440592023-01-26 21:01:51 +01006 * Copyright (C) 2016-2019 Glider bvba
7 * Copyright (C) 2018-2019 Renesas Electronics Corp.
Marek Vasut78414832019-03-04 21:38:10 +01008 *
9 * Based on r8a7795-cpg-mssr.c
10 *
11 * Copyright (C) 2015 Glider bvba
12 * Copyright (C) 2015 Renesas Electronics Corp.
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010013 */
14
15#include <common.h>
16#include <clk-uclass.h>
17#include <dm.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060018#include <linux/bitops.h>
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010019
20#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
21
22#include "renesas-cpg-mssr.h"
Marek Vasut7ef12c22018-01-08 17:09:45 +010023#include "rcar-gen3-cpg.h"
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010024
Marek Vasutb9234192018-01-08 16:05:28 +010025enum clk_ids {
26 /* Core Clock Outputs exported to DT */
27 LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
28
29 /* External Input Clocks */
30 CLK_EXTAL,
31 CLK_EXTALR,
32
33 /* Internal Core Clocks */
34 CLK_MAIN,
35 CLK_PLL0,
36 CLK_PLL1,
37 CLK_PLL2,
38 CLK_PLL3,
39 CLK_PLL4,
40 CLK_PLL1_DIV2,
41 CLK_PLL1_DIV4,
42 CLK_S0,
43 CLK_S1,
44 CLK_S2,
45 CLK_S3,
46 CLK_SDSRC,
Marek Vasutb9234192018-01-08 16:05:28 +010047 CLK_SSPSRC,
Marek Vasut0e8dcb72021-04-25 21:10:40 +020048 CLK_RPCSRC,
Marek Vasutb9234192018-01-08 16:05:28 +010049 CLK_RINT,
50
51 /* Module Clocks */
52 MOD_CLK_BASE
53};
54
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010055static const struct cpg_core_clk r8a7796_core_clks[] = {
56 /* External Clock Inputs */
57 DEF_INPUT("extal", CLK_EXTAL),
58 DEF_INPUT("extalr", CLK_EXTALR),
59
60 /* Internal Core Clocks */
61 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
62 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
63 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
64 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
65 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
66 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
67
68 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
69 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
70 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
71 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
72 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
73 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
Marek Vasut0e8dcb72021-04-25 21:10:40 +020075
Marek Vasutfd440592023-01-26 21:01:51 +010076 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010077
Marek Vasut78414832019-03-04 21:38:10 +010078 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
79
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010080 /* Core Clock Outputs */
Marek Vasut0e8dcb72021-04-25 21:10:40 +020081 DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
82 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010083 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
84 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
85 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
86 DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
87 DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
88 DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
89 DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
90 DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
91 DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
92 DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
93 DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
94 DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
95 DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
96 DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
97 DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
98 DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
99 DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
100 DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
101 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
102 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
103
Marek Vasutfd440592023-01-26 21:01:51 +0100104 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074),
105 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078),
106 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268),
107 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c),
108 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
109 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
110 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
111 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
112
113 DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
114 DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100115
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100116 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200117 DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100118 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
Marek Vasut78414832019-03-04 21:38:10 +0100119 DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100120
Marek Vasut78414832019-03-04 21:38:10 +0100121 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
122 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
123 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
124 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125
126 DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100127
128 DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
129};
130
131static const struct mssr_mod_clk r8a7796_mod_clks[] = {
Marek Vasut78414832019-03-04 21:38:10 +0100132 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200133 DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
134 DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
135 DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2),
136 DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2),
137 DEF_MOD("tmu0", 125, R8A7796_CLK_CP),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100138 DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
139 DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
140 DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
141 DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
142 DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
143 DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
144 DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
145 DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
146 DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200147 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
148 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100149 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200150 DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100151 DEF_MOD("cmt3", 300, R8A7796_CLK_R),
152 DEF_MOD("cmt2", 301, R8A7796_CLK_R),
153 DEF_MOD("cmt1", 302, R8A7796_CLK_R),
154 DEF_MOD("cmt0", 303, R8A7796_CLK_R),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200155 DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100156 DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
157 DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
158 DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
159 DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
160 DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
161 DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
162 DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
163 DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
164 DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
165 DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
166 DEF_MOD("rwdt", 402, R8A7796_CLK_R),
167 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
Marek Vasut78414832019-03-04 21:38:10 +0100168 DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200169 DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
170 DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
171 DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
172 DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
173 DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
174 DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
175 DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
176 DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
177 DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
178 DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100179 DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
180 DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
181 DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
182 DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
183 DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
184 DEF_MOD("thermal", 522, R8A7796_CLK_CP),
185 DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
186 DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
187 DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
188 DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
189 DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
190 DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
191 DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
192 DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
193 DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
194 DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
195 DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
196 DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
197 DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
198 DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200199 DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
200 DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
201 DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
202 DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1),
203 DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1),
204 DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100205 DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
206 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
207 DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
208 DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
209 DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
210 DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
211 DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
Marek Vasutfd440592023-01-26 21:01:51 +0100212 DEF_MOD("mlp", 802, R8A7796_CLK_S2D1),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100213 DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
214 DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
215 DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
216 DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
217 DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
218 DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
219 DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
220 DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
221 DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
222 DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
223 DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
224 DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
225 DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
226 DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
227 DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
228 DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
229 DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
230 DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
231 DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
232 DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
233 DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
234 DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
Marek Vasut0e8dcb72021-04-25 21:10:40 +0200235 DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100236 DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
237 DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
238 DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
239 DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
240 DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
241 DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
242 DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
243 DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
244 DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
245 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
246 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
247 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
248 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
249 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
250 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
251 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
252 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
253 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
254 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
255 DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
256 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
257 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
258 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
259 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
260 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
261 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
262 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
263 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
264 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
265 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
266 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
267 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
268 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
269 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
270};
271
Marek Vasut28f90042018-01-16 19:23:17 +0100272/*
273 * CPG Clock Data
274 */
275
276/*
Marek Vasut78414832019-03-04 21:38:10 +0100277 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
Marek Vasut28f90042018-01-16 19:23:17 +0100278 * 14 13 19 17 (MHz)
Marek Vasut78414832019-03-04 21:38:10 +0100279 *-------------------------------------------------------------------------
280 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
281 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
Marek Vasut28f90042018-01-16 19:23:17 +0100282 * 0 0 1 0 Prohibited setting
Marek Vasut78414832019-03-04 21:38:10 +0100283 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
284 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
285 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
Marek Vasut28f90042018-01-16 19:23:17 +0100286 * 0 1 1 0 Prohibited setting
Marek Vasut78414832019-03-04 21:38:10 +0100287 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
288 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
289 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
Marek Vasut28f90042018-01-16 19:23:17 +0100290 * 1 0 1 0 Prohibited setting
Marek Vasut78414832019-03-04 21:38:10 +0100291 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
292 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
293 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
Marek Vasut28f90042018-01-16 19:23:17 +0100294 * 1 1 1 0 Prohibited setting
Marek Vasut78414832019-03-04 21:38:10 +0100295 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
Marek Vasut28f90042018-01-16 19:23:17 +0100296 */
297#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
298 (((md) & BIT(13)) >> 11) | \
299 (((md) & BIT(19)) >> 18) | \
300 (((md) & BIT(17)) >> 17))
301
302static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
Marek Vasut78414832019-03-04 21:38:10 +0100303 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
304 { 1, 192, 1, 192, 1, 16, },
305 { 1, 192, 1, 128, 1, 16, },
306 { 0, /* Prohibited setting */ },
307 { 1, 192, 1, 192, 1, 16, },
308 { 1, 160, 1, 160, 1, 19, },
309 { 1, 160, 1, 106, 1, 19, },
310 { 0, /* Prohibited setting */ },
311 { 1, 160, 1, 160, 1, 19, },
312 { 1, 128, 1, 128, 1, 24, },
313 { 1, 128, 1, 84, 1, 24, },
314 { 0, /* Prohibited setting */ },
315 { 1, 128, 1, 128, 1, 24, },
316 { 2, 192, 1, 192, 1, 32, },
317 { 2, 192, 1, 128, 1, 32, },
318 { 0, /* Prohibited setting */ },
319 { 2, 192, 1, 192, 1, 32, },
Marek Vasut28f90042018-01-16 19:23:17 +0100320};
321
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100322static const struct mstp_stop_table r8a7796_mstp_table[] = {
Marek Vasut2eb56a12018-01-15 00:58:35 +0100323 { 0x00200000, 0x0, 0x00200000, 0 },
Marek Vasut22f9fc72020-04-25 14:57:45 +0200324 { 0xd3e813a0, 0x0, 0xd3e813a0, 0 },
325 { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
326 { 0xd00c7cdf, 0x400, 0xd00c7cdf, 0 },
327 { 0x80000004, 0x180, 0x80000004, 0 },
328 { 0x40dfff46, 0x0, 0x40dfff46, 0 },
329 { 0x84ea888e, 0x0, 0x84ea888e, 0 },
330 { 0x29df5e1c, 0x0, 0x29df5e1c, 0 },
331 { 0x01c01ff7, 0x0, 0x01f01ff7, 0 },
332 { 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
333 { 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
334 { 0x00000000, 0x0, 0x00000000, 0 },
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100335};
336
Marek Vasut28f90042018-01-16 19:23:17 +0100337static const void *r8a7796_get_pll_config(const u32 cpg_mode)
338{
339 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
340}
341
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100342static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
343 .core_clk = r8a7796_core_clks,
344 .core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
345 .mod_clk = r8a7796_mod_clks,
346 .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
347 .mstp_table = r8a7796_mstp_table,
348 .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
349 .reset_node = "renesas,r8a7796-rst",
Marek Vasut814217e2021-04-25 21:53:05 +0200350 .reset_modemr_offset = CPG_RST_MODEMR,
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100351 .extalr_node = "extalr",
Marek Vasutb9234192018-01-08 16:05:28 +0100352 .mod_clk_base = MOD_CLK_BASE,
353 .clk_extal_id = CLK_EXTAL,
354 .clk_extalr_id = CLK_EXTALR,
Marek Vasut28f90042018-01-16 19:23:17 +0100355 .get_pll_config = r8a7796_get_pll_config,
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100356};
357
Hai Phamf144d502023-01-26 21:02:02 +0100358static const struct cpg_mssr_info r8a77961_cpg_mssr_info = {
359 .core_clk = r8a7796_core_clks,
360 .core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
361 .mod_clk = r8a7796_mod_clks,
362 .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
363 .mstp_table = r8a7796_mstp_table,
364 .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
365 .reset_node = "renesas,r8a77961-rst",
366 .extalr_node = "extalr",
367 .mod_clk_base = MOD_CLK_BASE,
368 .clk_extal_id = CLK_EXTAL,
369 .clk_extalr_id = CLK_EXTALR,
370 .get_pll_config = r8a7796_get_pll_config,
371};
372
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100373static const struct udevice_id r8a7796_clk_ids[] = {
374 {
375 .compatible = "renesas,r8a7796-cpg-mssr",
376 .data = (ulong)&r8a7796_cpg_mssr_info,
377 },
Hai Phamf144d502023-01-26 21:02:02 +0100378 {
379 .compatible = "renesas,r8a77961-cpg-mssr",
380 .data = (ulong)&r8a77961_cpg_mssr_info,
381 },
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100382 { }
383};
384
385U_BOOT_DRIVER(clk_r8a7796) = {
386 .name = "clk_r8a7796",
387 .id = UCLASS_CLK,
388 .of_match = r8a7796_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700389 .priv_auto = sizeof(struct gen3_clk_priv),
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100390 .ops = &gen3_clk_ops,
391 .probe = gen3_clk_probe,
392 .remove = gen3_clk_remove,
393};