| TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * mcf5329.h -- Definitions for Freescale Coldfire 5329 |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef mcf5329_h |
| 27 | #define mcf5329_h |
| 28 | /****************************************************************************/ |
| 29 | |
| 30 | /********************************************************************* |
| 31 | * System Control Module (SCM) |
| 32 | *********************************************************************/ |
| 33 | /* Bit definitions and macros for SCM_MPR */ |
| 34 | #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) |
| 35 | #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) |
| 36 | #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) |
| 37 | #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) |
| 38 | #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) |
| 39 | #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) |
| 40 | #define MPROT_MTR 4 |
| 41 | #define MPROT_MTW 2 |
| 42 | #define MPROT_MPL 1 |
| 43 | |
| 44 | /* Bit definitions and macros for SCM_BMT */ |
| 45 | #define BMT_BME (0x08) |
| 46 | #define BMT_8 (0x07) |
| 47 | #define BMT_16 (0x06) |
| 48 | #define BMT_32 (0x05) |
| 49 | #define BMT_64 (0x04) |
| 50 | #define BMT_128 (0x03) |
| 51 | #define BMT_256 (0x02) |
| 52 | #define BMT_512 (0x01) |
| 53 | #define BMT_1024 (0x00) |
| 54 | |
| 55 | /* Bit definitions and macros for SCM_PACRA */ |
| 56 | #define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) |
| 57 | #define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) |
| 58 | #define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) |
| 59 | #define PACR_SP 4 |
| 60 | #define PACR_WP 2 |
| 61 | #define PACR_TP 1 |
| 62 | |
| 63 | /* Bit definitions and macros for SCM_PACRB */ |
| 64 | #define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) |
| 65 | #define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12) |
| 66 | |
| 67 | /* Bit definitions and macros for SCM_PACRC */ |
| 68 | #define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28) |
| 69 | #define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24) |
| 70 | #define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20) |
| 71 | #define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16) |
| 72 | #define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8) |
| 73 | #define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4) |
| 74 | #define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0) |
| 75 | |
| 76 | /* Bit definitions and macros for SCM_PACRD */ |
| 77 | #define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28) |
| 78 | #define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24) |
| 79 | #define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20) |
| 80 | #define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12) |
| 81 | #define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8) |
| 82 | #define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4) |
| 83 | #define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0) |
| 84 | |
| 85 | /* Bit definitions and macros for SCM_PACRE */ |
| 86 | #define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28) |
| 87 | #define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24) |
| 88 | #define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20) |
| 89 | #define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16) |
| 90 | #define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12) |
| 91 | #define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8) |
| 92 | #define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4) |
| 93 | |
| 94 | /* Bit definitions and macros for SCM_PACRF */ |
| 95 | #define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28) |
| 96 | #define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24) |
| 97 | #define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20) |
| 98 | #define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16) |
| 99 | #define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12) |
| 100 | #define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8) |
| 101 | #define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4) |
| 102 | #define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0) |
| 103 | |
| 104 | /* Bit definitions and macros for SCM_PACRG */ |
| 105 | #define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28) |
| 106 | |
| 107 | /* Bit definitions and macros for SCM_PACRH */ |
| 108 | #define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28) |
| 109 | #define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24) |
| 110 | #define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20) |
| 111 | |
| 112 | /* PACRn Assignments */ |
| 113 | #define PACR0(x) SCM_PACRA_PACR0(x) |
| 114 | #define PACR1(x) SCM_PACRA_PACR1(x) |
| 115 | #define PACR2(x) SCM_PACRA_PACR2(x) |
| 116 | #define PACR8(x) SCM_PACRB_PACR8(x) |
| 117 | #define PACR12(x) SCM_PACRB_PACR12(x) |
| 118 | #define PACR16(x) SCM_PACRC_PACR16(x) |
| 119 | #define PACR17(x) SCM_PACRC_PACR17(x) |
| 120 | #define PACR18(x) SCM_PACRC_PACR18(x) |
| 121 | #define PACR19(x) SCM_PACRC_PACR19(x) |
| 122 | #define PACR21(x) SCM_PACRC_PACR21(x) |
| 123 | #define PACR22(x) SCM_PACRC_PACR22(x) |
| 124 | #define PACR23(x) SCM_PACRC_PACR23(x) |
| 125 | #define PACR24(x) SCM_PACRD_PACR24(x) |
| 126 | #define PACR25(x) SCM_PACRD_PACR25(x) |
| 127 | #define PACR26(x) SCM_PACRD_PACR26(x) |
| 128 | #define PACR28(x) SCM_PACRD_PACR28(x) |
| 129 | #define PACR29(x) SCM_PACRD_PACR29(x) |
| 130 | #define PACR30(x) SCM_PACRD_PACR30(x) |
| 131 | #define PACR31(x) SCM_PACRD_PACR31(x) |
| 132 | #define PACR32(x) SCM_PACRE_PACR32(x) |
| 133 | #define PACR33(x) SCM_PACRE_PACR33(x) |
| 134 | #define PACR34(x) SCM_PACRE_PACR34(x) |
| 135 | #define PACR35(x) SCM_PACRE_PACR35(x) |
| 136 | #define PACR36(x) SCM_PACRE_PACR36(x) |
| 137 | #define PACR37(x) SCM_PACRE_PACR37(x) |
| 138 | #define PACR38(x) SCM_PACRE_PACR38(x) |
| 139 | #define PACR40(x) SCM_PACRF_PACR40(x) |
| 140 | #define PACR41(x) SCM_PACRF_PACR41(x) |
| 141 | #define PACR42(x) SCM_PACRF_PACR42(x) |
| 142 | #define PACR43(x) SCM_PACRF_PACR43(x) |
| 143 | #define PACR44(x) SCM_PACRF_PACR44(x) |
| 144 | #define PACR45(x) SCM_PACRF_PACR45(x) |
| 145 | #define PACR46(x) SCM_PACRF_PACR46(x) |
| 146 | #define PACR47(x) SCM_PACRF_PACR47(x) |
| 147 | #define PACR48(x) SCM_PACRG_PACR48(x) |
| 148 | #define PACR56(x) SCM_PACRH_PACR56(x) |
| 149 | #define PACR57(x) SCM_PACRH_PACR57(x) |
| 150 | #define PACR58(x) SCM_PACRH_PACR58(x) |
| 151 | |
| 152 | /* Bit definitions and macros for SCM_CWCR */ |
| 153 | #define CWCR_RO (0x8000) |
| 154 | #define CWCR_CWR_WH (0x0100) |
| 155 | #define CWCR_CWE (0x0080) |
| 156 | #define CWRI_WINDOW (0x0060) |
| 157 | #define CWRI_RESET (0x0040) |
| 158 | #define CWRI_INT_RESET (0x0020) |
| 159 | #define CWRI_INT (0x0000) |
| 160 | #define CWCR_CWT(x) (((x)&0x001F)) |
| 161 | |
| 162 | /* Bit definitions and macros for SCM_ISR */ |
| 163 | #define SCMISR_CFEI (0x02) |
| 164 | #define SCMISR_CWIC (0x01) |
| 165 | |
| 166 | /* Bit definitions and macros for SCM_BCR */ |
| 167 | #define BCR_GBR (0x00000200) |
| 168 | #define BCR_GBW (0x00000100) |
| 169 | #define BCR_S7 (0x00000080) |
| 170 | #define BCR_S6 (0x00000040) |
| 171 | #define BCR_S4 (0x00000010) |
| 172 | #define BCR_S1 (0x00000002) |
| 173 | |
| 174 | /* Bit definitions and macros for SCM_CFIER */ |
| 175 | #define CFIER_ECFEI (0x01) |
| 176 | |
| 177 | /* Bit definitions and macros for SCM_CFLOC */ |
| 178 | #define CFLOC_LOC (0x80) |
| 179 | |
| 180 | /* Bit definitions and macros for SCM_CFATR */ |
| 181 | #define CFATR_WRITE (0x80) |
| 182 | #define CFATR_SZ32 (0x20) |
| 183 | #define CFATR_SZ16 (0x10) |
| 184 | #define CFATR_SZ08 (0x00) |
| 185 | #define CFATR_CACHE (0x08) |
| 186 | #define CFATR_MODE (0x02) |
| 187 | #define CFATR_TYPE (0x01) |
| 188 | |
| 189 | /********************************************************************* |
| 190 | * |
| 191 | * Random Number Generator (RNG) |
| 192 | * |
| 193 | *********************************************************************/ |
| 194 | /* Bit definitions and macros for RNG_RNGCR */ |
| 195 | #define RNGCR_CI (0x00000008) |
| 196 | #define RNGCR_IM (0x00000004) |
| 197 | #define RNGCR_HA (0x00000002) |
| 198 | #define RNGCR_GO (0x00000001) |
| 199 | |
| 200 | /* Bit definitions and macros for RNG_RNGSR */ |
| 201 | #define RNGSR_OFS(x) (((x)&0xFF)<<16) |
| 202 | #define RNGSR_OFL(x) (((x)&0xFF)<<8) |
| 203 | #define RNGSR_EI (0x00000008) |
| 204 | #define RNGSR_FUF (0x00000004) |
| 205 | #define RNGSR_LRS (0x00000002) |
| 206 | #define RNGSR_SV (0x00000001) |
| 207 | |
| 208 | /********************************************************************* |
| 209 | * FlexBus Chip Selects (FBCS) |
| 210 | *********************************************************************/ |
| 211 | /* Bit definitions and macros for FBCS_CSAR */ |
| 212 | #define CSAR_BA(x) (((x)&0xFFFF)<<16) |
| 213 | |
| 214 | /* Bit definitions and macros for FBCS_CSMR */ |
| 215 | #define CSMR_BAM(x) (((x)&0xFFFF)<<16) |
| 216 | #define CSMR_BAM_4G (0xFFFF0000) |
| 217 | #define CSMR_BAM_2G (0x7FFF0000) |
| 218 | #define CSMR_BAM_1G (0x3FFF0000) |
| 219 | #define CSMR_BAM_1024M (0x3FFF0000) |
| 220 | #define CSMR_BAM_512M (0x1FFF0000) |
| 221 | #define CSMR_BAM_256M (0x0FFF0000) |
| 222 | #define CSMR_BAM_128M (0x07FF0000) |
| 223 | #define CSMR_BAM_64M (0x03FF0000) |
| 224 | #define CSMR_BAM_32M (0x01FF0000) |
| 225 | #define CSMR_BAM_16M (0x00FF0000) |
| 226 | #define CSMR_BAM_8M (0x007F0000) |
| 227 | #define CSMR_BAM_4M (0x003F0000) |
| 228 | #define CSMR_BAM_2M (0x001F0000) |
| 229 | #define CSMR_BAM_1M (0x000F0000) |
| 230 | #define CSMR_BAM_1024K (0x000F0000) |
| 231 | #define CSMR_BAM_512K (0x00070000) |
| 232 | #define CSMR_BAM_256K (0x00030000) |
| 233 | #define CSMR_BAM_128K (0x00010000) |
| 234 | #define CSMR_BAM_64K (0x00000000) |
| 235 | #define CSMR_WP (0x00000100) |
| 236 | #define CSMR_V (0x00000001) |
| 237 | |
| 238 | /* Bit definitions and macros for FBCS_CSCR */ |
| 239 | #define CSCR_SWS(x) (((x)&0x3F)<<26) |
| 240 | #define CSCR_ASET(x) (((x)&0x03)<<20) |
| 241 | #define CSCR_SWSEN (0x00800000) |
| 242 | #define CSCR_ASET_4CLK (0x00300000) |
| 243 | #define CSCR_ASET_3CLK (0x00200000) |
| 244 | #define CSCR_ASET_2CLK (0x00100000) |
| 245 | #define CSCR_ASET_1CLK (0x00000000) |
| 246 | #define CSCR_RDAH(x) (((x)&0x03)<<18) |
| 247 | #define CSCR_RDAH_4CYC (0x000C0000) |
| 248 | #define CSCR_RDAH_3CYC (0x00080000) |
| 249 | #define CSCR_RDAH_2CYC (0x00040000) |
| 250 | #define CSCR_RDAH_1CYC (0x00000000) |
| 251 | #define CSCR_WRAH(x) (((x)&0x03)<<16) |
| 252 | #define CSCR_WDAH_4CYC (0x00003000) |
| 253 | #define CSCR_WDAH_3CYC (0x00002000) |
| 254 | #define CSCR_WDAH_2CYC (0x00001000) |
| 255 | #define CSCR_WDAH_1CYC (0x00000000) |
| 256 | #define CSCR_WS(x) (((x)&0x3F)<<10) |
| 257 | #define CSCR_SBM (0x00000200) |
| 258 | #define CSCR_AA (0x00000100) |
| 259 | #define CSCR_PS_MASK (0x000000C0) |
| 260 | #define CSCR_PS_32 (0x00000000) |
| 261 | #define CSCR_PS_16 (0x00000080) |
| 262 | #define CSCR_PS_8 (0x00000040) |
| 263 | #define CSCR_BEM (0x00000020) |
| 264 | #define CSCR_BSTR (0x00000010) |
| 265 | #define CSCR_BSTW (0x00000008) |
| 266 | |
| 267 | /********************************************************************* |
| 268 | * FlexCAN Module (CAN) |
| 269 | *********************************************************************/ |
| 270 | /* Bit definitions and macros for CAN_CANMCR */ |
| 271 | #define CANMCR_MDIS (0x80000000) |
| 272 | #define CANMCR_FRZ (0x40000000) |
| 273 | #define CANMCR_HALT (0x10000000) |
| 274 | #define CANMCR_NORDY (0x08000000) |
| 275 | #define CANMCR_SOFTRST (0x02000000) |
| 276 | #define CANMCR_FRZACK (0x01000000) |
| 277 | #define CANMCR_SUPV (0x00800000) |
| 278 | #define CANMCR_LPMACK (0x00100000) |
| 279 | #define CANMCR_MAXMB(x) (((x)&0x0F)) |
| 280 | |
| 281 | /* Bit definitions and macros for CAN_CANCTRL */ |
| 282 | #define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) |
| 283 | #define CANCTRL_RJW(x) (((x)&0x03)<<22) |
| 284 | #define CANCTRL_PSEG1(x) (((x)&0x07)<<19) |
| 285 | #define CANCTRL_PSEG2(x) (((x)&0x07)<<16) |
| 286 | #define CANCTRL_BOFFMSK (0x00008000) |
| 287 | #define CANCTRL_ERRMSK (0x00004000) |
| 288 | #define CANCTRL_CLKSRC (0x00002000) |
| 289 | #define CANCTRL_LPB (0x00001000) |
| 290 | #define CANCTRL_SMP (0x00000080) |
| 291 | #define CANCTRL_BOFFREC (0x00000040) |
| 292 | #define CANCTRL_TSYNC (0x00000020) |
| 293 | #define CANCTRL_LBUF (0x00000010) |
| 294 | #define CANCTRL_LOM (0x00000008) |
| 295 | #define CANCTRL_PROPSEG(x) (((x)&0x07)) |
| 296 | |
| 297 | /* Bit definitions and macros for CAN_TIMER */ |
| 298 | #define TIMER_TIMER(x) ((x)&0xFFFF) |
| 299 | |
| 300 | /* Bit definitions and macros for CAN_RXGMASK */ |
| 301 | #define RXGMASK_MI(x) ((x)&0x1FFFFFFF) |
| 302 | |
| 303 | /* Bit definitions and macros for CAN_ERRCNT */ |
| 304 | #define ERRCNT_TXECTR(x) (((x)&0xFF)) |
| 305 | #define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) |
| 306 | |
| 307 | /* Bit definitions and macros for CAN_ERRSTAT */ |
| 308 | #define ERRSTAT_BITERR1 (0x00008000) |
| 309 | #define ERRSTAT_BITERR0 (0x00004000) |
| 310 | #define ERRSTAT_ACKERR (0x00002000) |
| 311 | #define ERRSTAT_CRCERR (0x00001000) |
| 312 | #define ERRSTAT_FRMERR (0x00000800) |
| 313 | #define ERRSTAT_STFERR (0x00000400) |
| 314 | #define ERRSTAT_TXWRN (0x00000200) |
| 315 | #define ERRSTAT_RXWRN (0x00000100) |
| 316 | #define ERRSTAT_IDLE (0x00000080) |
| 317 | #define ERRSTAT_TXRX (0x00000040) |
| 318 | #define ERRSTAT_FLT_BUSOFF (0x00000020) |
| 319 | #define ERRSTAT_FLT_PASSIVE (0x00000010) |
| 320 | #define ERRSTAT_FLT_ACTIVE (0x00000000) |
| 321 | #define ERRSTAT_BOFFINT (0x00000004) |
| 322 | #define ERRSTAT_ERRINT (0x00000002) |
| 323 | #define ERRSTAT_WAKINT (0x00000001) |
| 324 | |
| 325 | /* Bit definitions and macros for CAN_IMASK */ |
| 326 | #define IMASK_BUF15M (0x00008000) |
| 327 | #define IMASK_BUF14M (0x00004000) |
| 328 | #define IMASK_BUF13M (0x00002000) |
| 329 | #define IMASK_BUF12M (0x00001000) |
| 330 | #define IMASK_BUF11M (0x00000800) |
| 331 | #define IMASK_BUF10M (0x00000400) |
| 332 | #define IMASK_BUF9M (0x00000200) |
| 333 | #define IMASK_BUF8M (0x00000100) |
| 334 | #define IMASK_BUF7M (0x00000080) |
| 335 | #define IMASK_BUF6M (0x00000040) |
| 336 | #define IMASK_BUF5M (0x00000020) |
| 337 | #define IMASK_BUF4M (0x00000010) |
| 338 | #define IMASK_BUF3M (0x00000008) |
| 339 | #define IMASK_BUF2M (0x00000004) |
| 340 | #define IMASK_BUF1M (0x00000002) |
| 341 | #define IMASK_BUF0M (0x00000001) |
| 342 | |
| 343 | /* Bit definitions and macros for CAN_IFLAG */ |
| 344 | #define IFLAG_BUF15I (0x00008000) |
| 345 | #define IFLAG_BUF14I (0x00004000) |
| 346 | #define IFLAG_BUF13I (0x00002000) |
| 347 | #define IFLAG_BUF12I (0x00001000) |
| 348 | #define IFLAG_BUF11I (0x00000800) |
| 349 | #define IFLAG_BUF10I (0x00000400) |
| 350 | #define IFLAG_BUF9I (0x00000200) |
| 351 | #define IFLAG_BUF8I (0x00000100) |
| 352 | #define IFLAG_BUF7I (0x00000080) |
| 353 | #define IFLAG_BUF6I (0x00000040) |
| 354 | #define IFLAG_BUF5I (0x00000020) |
| 355 | #define IFLAG_BUF4I (0x00000010) |
| 356 | #define IFLAG_BUF3I (0x00000008) |
| 357 | #define IFLAG_BUF2I (0x00000004) |
| 358 | #define IFLAG_BUF1I (0x00000002) |
| 359 | #define IFLAG_BUF0I (0x00000001) |
| 360 | |
| 361 | /********************************************************************* |
| 362 | * Interrupt Controller (INTC) |
| 363 | *********************************************************************/ |
| 364 | #define INTC0_EPORT INTC_IPRL_INT1 |
| 365 | |
| 366 | #define INT0_LO_RSVD0 (0) |
| 367 | #define INT0_LO_EPORT1 (1) |
| 368 | #define INT0_LO_EPORT2 (2) |
| 369 | #define INT0_LO_EPORT3 (3) |
| 370 | #define INT0_LO_EPORT4 (4) |
| 371 | #define INT0_LO_EPORT5 (5) |
| 372 | #define INT0_LO_EPORT6 (6) |
| 373 | #define INT0_LO_EPORT7 (7) |
| 374 | #define INT0_LO_EDMA_00 (8) |
| 375 | #define INT0_LO_EDMA_01 (9) |
| 376 | #define INT0_LO_EDMA_02 (10) |
| 377 | #define INT0_LO_EDMA_03 (11) |
| 378 | #define INT0_LO_EDMA_04 (12) |
| 379 | #define INT0_LO_EDMA_05 (13) |
| 380 | #define INT0_LO_EDMA_06 (14) |
| 381 | #define INT0_LO_EDMA_07 (15) |
| 382 | #define INT0_LO_EDMA_08 (16) |
| 383 | #define INT0_LO_EDMA_09 (17) |
| 384 | #define INT0_LO_EDMA_10 (18) |
| 385 | #define INT0_LO_EDMA_11 (19) |
| 386 | #define INT0_LO_EDMA_12 (20) |
| 387 | #define INT0_LO_EDMA_13 (21) |
| 388 | #define INT0_LO_EDMA_14 (22) |
| 389 | #define INT0_LO_EDMA_15 (23) |
| 390 | #define INT0_LO_EDMA_ERR (24) |
| 391 | #define INT0_LO_SCM (25) |
| 392 | #define INT0_LO_UART0 (26) |
| 393 | #define INT0_LO_UART1 (27) |
| 394 | #define INT0_LO_UART2 (28) |
| 395 | #define INT0_LO_RSVD1 (29) |
| 396 | #define INT0_LO_I2C (30) |
| 397 | #define INT0_LO_QSPI (31) |
| 398 | #define INT0_HI_DTMR0 (32) |
| 399 | #define INT0_HI_DTMR1 (33) |
| 400 | #define INT0_HI_DTMR2 (34) |
| 401 | #define INT0_HI_DTMR3 (35) |
| 402 | #define INT0_HI_FEC_TXF (36) |
| 403 | #define INT0_HI_FEC_TXB (37) |
| 404 | #define INT0_HI_FEC_UN (38) |
| 405 | #define INT0_HI_FEC_RL (39) |
| 406 | #define INT0_HI_FEC_RXF (40) |
| 407 | #define INT0_HI_FEC_RXB (41) |
| 408 | #define INT0_HI_FEC_MII (42) |
| 409 | #define INT0_HI_FEC_LC (43) |
| 410 | #define INT0_HI_FEC_HBERR (44) |
| 411 | #define INT0_HI_FEC_GRA (45) |
| 412 | #define INT0_HI_FEC_EBERR (46) |
| 413 | #define INT0_HI_FEC_BABT (47) |
| 414 | #define INT0_HI_FEC_BABR (48) |
| 415 | /* 49 - 61 Reserved */ |
| 416 | #define INT0_HI_SCM (62) |
| 417 | |
| 418 | /*#define INT1_HI_ */ |
| 419 | |
| 420 | /* Bit definitions and macros for INTC_IPRH */ |
| 421 | #define INTC_IPRH_INT63 (0x80000000) |
| 422 | #define INTC_IPRH_INT62 (0x40000000) |
| 423 | #define INTC_IPRH_INT61 (0x20000000) |
| 424 | #define INTC_IPRH_INT60 (0x10000000) |
| 425 | #define INTC_IPRH_INT59 (0x08000000) |
| 426 | #define INTC_IPRH_INT58 (0x04000000) |
| 427 | #define INTC_IPRH_INT57 (0x02000000) |
| 428 | #define INTC_IPRH_INT56 (0x01000000) |
| 429 | #define INTC_IPRH_INT55 (0x00800000) |
| 430 | #define INTC_IPRH_INT54 (0x00400000) |
| 431 | #define INTC_IPRH_INT53 (0x00200000) |
| 432 | #define INTC_IPRH_INT52 (0x00100000) |
| 433 | #define INTC_IPRH_INT51 (0x00080000) |
| 434 | #define INTC_IPRH_INT50 (0x00040000) |
| 435 | #define INTC_IPRH_INT49 (0x00020000) |
| 436 | #define INTC_IPRH_INT48 (0x00010000) |
| 437 | #define INTC_IPRH_INT47 (0x00008000) |
| 438 | #define INTC_IPRH_INT46 (0x00004000) |
| 439 | #define INTC_IPRH_INT45 (0x00002000) |
| 440 | #define INTC_IPRH_INT44 (0x00001000) |
| 441 | #define INTC_IPRH_INT43 (0x00000800) |
| 442 | #define INTC_IPRH_INT42 (0x00000400) |
| 443 | #define INTC_IPRH_INT41 (0x00000200) |
| 444 | #define INTC_IPRH_INT40 (0x00000100) |
| 445 | #define INTC_IPRH_INT39 (0x00000080) |
| 446 | #define INTC_IPRH_INT38 (0x00000040) |
| 447 | #define INTC_IPRH_INT37 (0x00000020) |
| 448 | #define INTC_IPRH_INT36 (0x00000010) |
| 449 | #define INTC_IPRH_INT35 (0x00000008) |
| 450 | #define INTC_IPRH_INT34 (0x00000004) |
| 451 | #define INTC_IPRH_INT33 (0x00000002) |
| 452 | #define INTC_IPRH_INT32 (0x00000001) |
| 453 | |
| 454 | /* Bit definitions and macros for INTC_IPRL */ |
| 455 | #define INTC_IPRL_INT31 (0x80000000) |
| 456 | #define INTC_IPRL_INT30 (0x40000000) |
| 457 | #define INTC_IPRL_INT29 (0x20000000) |
| 458 | #define INTC_IPRL_INT28 (0x10000000) |
| 459 | #define INTC_IPRL_INT27 (0x08000000) |
| 460 | #define INTC_IPRL_INT26 (0x04000000) |
| 461 | #define INTC_IPRL_INT25 (0x02000000) |
| 462 | #define INTC_IPRL_INT24 (0x01000000) |
| 463 | #define INTC_IPRL_INT23 (0x00800000) |
| 464 | #define INTC_IPRL_INT22 (0x00400000) |
| 465 | #define INTC_IPRL_INT21 (0x00200000) |
| 466 | #define INTC_IPRL_INT20 (0x00100000) |
| 467 | #define INTC_IPRL_INT19 (0x00080000) |
| 468 | #define INTC_IPRL_INT18 (0x00040000) |
| 469 | #define INTC_IPRL_INT17 (0x00020000) |
| 470 | #define INTC_IPRL_INT16 (0x00010000) |
| 471 | #define INTC_IPRL_INT15 (0x00008000) |
| 472 | #define INTC_IPRL_INT14 (0x00004000) |
| 473 | #define INTC_IPRL_INT13 (0x00002000) |
| 474 | #define INTC_IPRL_INT12 (0x00001000) |
| 475 | #define INTC_IPRL_INT11 (0x00000800) |
| 476 | #define INTC_IPRL_INT10 (0x00000400) |
| 477 | #define INTC_IPRL_INT9 (0x00000200) |
| 478 | #define INTC_IPRL_INT8 (0x00000100) |
| 479 | #define INTC_IPRL_INT7 (0x00000080) |
| 480 | #define INTC_IPRL_INT6 (0x00000040) |
| 481 | #define INTC_IPRL_INT5 (0x00000020) |
| 482 | #define INTC_IPRL_INT4 (0x00000010) |
| 483 | #define INTC_IPRL_INT3 (0x00000008) |
| 484 | #define INTC_IPRL_INT2 (0x00000004) |
| 485 | #define INTC_IPRL_INT1 (0x00000002) |
| 486 | #define INTC_IPRL_INT0 (0x00000001) |
| 487 | |
| 488 | /* Bit definitions and macros for INTC_ICONFIG */ |
| 489 | #define INTC_ICFG_ELVLPRI7 (0x8000) |
| 490 | #define INTC_ICFG_ELVLPRI6 (0x4000) |
| 491 | #define INTC_ICFG_ELVLPRI5 (0x2000) |
| 492 | #define INTC_ICFG_ELVLPRI4 (0x1000) |
| 493 | #define INTC_ICFG_ELVLPRI3 (0x0800) |
| 494 | #define INTC_ICFG_ELVLPRI2 (0x0400) |
| 495 | #define INTC_ICFG_ELVLPRI1 (0x0200) |
| 496 | #define INTC_ICFG_EMASK (0x0020) |
| 497 | |
| 498 | /* Bit definitions and macros for INTC_SIMR */ |
| 499 | #define INTC_SIMR_SALL (0x40) |
| 500 | #define INTC_SIMR_SIMR(x) ((x)&0x3F) |
| 501 | |
| 502 | /* Bit definitions and macros for INTC_CIMR */ |
| 503 | #define INTC_CIMR_CALL (0x40) |
| 504 | #define INTC_CIMR_CIMR(x) ((x)&0x3F) |
| 505 | |
| 506 | /* Bit definitions and macros for INTC_CLMASK */ |
| 507 | #define INTC_CLMASK_CLMASK(x) ((x)&0x0F) |
| 508 | |
| 509 | /* Bit definitions and macros for INTC_SLMASK */ |
| 510 | #define INTC_SLMASK_SLMASK(x) ((x)&0x0F) |
| 511 | |
| 512 | /* Bit definitions and macros for INTC_ICR */ |
| 513 | #define INTC_ICR_IL(x) ((x)&0x07) |
| 514 | |
| 515 | /********************************************************************* |
| 516 | * I2C Module (I2C) |
| 517 | *********************************************************************/ |
| 518 | /* Bit definitions and macros for I2C_AR */ |
| 519 | #define I2C_AR_ADR(x) (((x)&0x7F)<<1) |
| 520 | |
| 521 | /* Bit definitions and macros for I2C_FDR */ |
| 522 | #define I2C_FDR_IC(x) ((x)&0x3F) |
| 523 | |
| 524 | /* Bit definitions and macros for I2C_CR */ |
| 525 | #define I2C_CR_IEN (0x80) |
| 526 | #define I2C_CR_IIEN (0x40) |
| 527 | #define I2C_CR_MSTA (0x20) |
| 528 | #define I2C_CR_MTX (0x10) |
| 529 | #define I2C_CR_TXAK (0x08) |
| 530 | #define I2C_CR_RSTA (0x04) |
| 531 | |
| 532 | /* Bit definitions and macros for I2C_SR */ |
| 533 | #define I2C_SR_ICF (0x80) |
| 534 | #define I2C_SR_IAAS (0x40) |
| 535 | #define I2C_SR_IBB (0x20) |
| 536 | #define I2C_SR_IAL (0x10) |
| 537 | #define I2C_SR_SRW (0x04) |
| 538 | #define I2C_SR_IIF (0x02) |
| 539 | #define I2C_SR_RXAK (0x01) |
| 540 | |
| 541 | /* Bit definitions and macros for I2C_ICR */ |
| 542 | #define I2C_ICR_BNBE (0x08) |
| 543 | #define I2C_ICR_TE (0x04) |
| 544 | #define I2C_ICR_RE (0x02) |
| 545 | #define I2C_ICR_IE (0x01) |
| 546 | |
| 547 | /********************************************************************* |
| 548 | * Queued Serial Peripheral Interface (QSPI) |
| 549 | *********************************************************************/ |
| 550 | /* Bit definitions and macros for QSPI_QMR */ |
| 551 | #define QSPI_QMR_MSTR (0x8000) |
| 552 | #define QSPI_QMR_DOHIE (0x4000) |
| 553 | #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) |
| 554 | #define QSPI_QMR_CPOL (0x0200) |
| 555 | #define QSPI_QMR_CPHA (0x0100) |
| 556 | #define QSPI_QMR_BAUD(x) ((x)&0x00FF) |
| 557 | |
| 558 | /* Bit definitions and macros for QSPI_QDLYR */ |
| 559 | #define QSPI_QDLYR_SPE (0x8000) |
| 560 | #define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) |
| 561 | #define QSPI_QDLYR_DTL(x) ((x)&0x00FF) |
| 562 | |
| 563 | /* Bit definitions and macros for QSPI_QWR */ |
| 564 | #define QSPI_QWR_NEWQP(x) ((x)&0x000F) |
| 565 | #define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) |
| 566 | #define QSPI_QWR_CSIV (0x1000) |
| 567 | #define QSPI_QWR_WRTO (0x2000) |
| 568 | #define QSPI_QWR_WREN (0x4000) |
| 569 | #define QSPI_QWR_HALT (0x8000) |
| 570 | |
| 571 | /* Bit definitions and macros for QSPI_QIR */ |
| 572 | #define QSPI_QIR_WCEFB (0x8000) |
| 573 | #define QSPI_QIR_ABRTB (0x4000) |
| 574 | #define QSPI_QIR_ABRTL (0x1000) |
| 575 | #define QSPI_QIR_WCEFE (0x0800) |
| 576 | #define QSPI_QIR_ABRTE (0x0400) |
| 577 | #define QSPI_QIR_SPIFE (0x0100) |
| 578 | #define QSPI_QIR_WCEF (0x0008) |
| 579 | #define QSPI_QIR_ABRT (0x0004) |
| 580 | #define QSPI_QIR_SPIF (0x0001) |
| 581 | |
| 582 | /* Bit definitions and macros for QSPI_QAR */ |
| 583 | #define QSPI_QAR_ADDR(x) ((x)&0x003F) |
| 584 | #define QSPI_QAR_TRANS (0x0000) |
| 585 | #define QSPI_QAR_RECV (0x0010) |
| 586 | #define QSPI_QAR_CMD (0x0020) |
| 587 | |
| 588 | /* Bit definitions and macros for QSPI_QDR */ |
| 589 | #define QSPI_QDR_CONT (0x8000) |
| 590 | #define QSPI_QDR_BITSE (0x4000) |
| 591 | #define QSPI_QDR_DT (0x2000) |
| 592 | #define QSPI_QDR_DSCK (0x1000) |
| 593 | #define QSPI_QDR_QSPI_CS3 (0x0800) |
| 594 | #define QSPI_QDR_QSPI_CS2 (0x0400) |
| 595 | #define QSPI_QDR_QSPI_CS1 (0x0200) |
| 596 | #define QSPI_QDR_QSPI_CS0 (0x0100) |
| 597 | |
| 598 | /********************************************************************* |
| 599 | * Pulse Width Modulation (PWM) |
| 600 | *********************************************************************/ |
| 601 | /* Bit definitions and macros for PWM_E */ |
| 602 | #define PWM_EN_PWME7 (0x80) |
| 603 | #define PWM_EN_PWME5 (0x20) |
| 604 | #define PWM_EN_PWME3 (0x08) |
| 605 | #define PWM_EN_PWME1 (0x02) |
| 606 | |
| 607 | /* Bit definitions and macros for PWM_POL */ |
| 608 | #define PWM_POL_PPOL7 (0x80) |
| 609 | #define PWM_POL_PPOL5 (0x20) |
| 610 | #define PWM_POL_PPOL3 (0x08) |
| 611 | #define PWM_POL_PPOL1 (0x02) |
| 612 | |
| 613 | /* Bit definitions and macros for PWM_CLK */ |
| 614 | #define PWM_CLK_PCLK7 (0x80) |
| 615 | #define PWM_CLK_PCLK5 (0x20) |
| 616 | #define PWM_CLK_PCLK3 (0x08) |
| 617 | #define PWM_CLK_PCLK1 (0x02) |
| 618 | |
| 619 | /* Bit definitions and macros for PWM_PRCLK */ |
| 620 | #define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4) |
| 621 | #define PWM_PRCLK_PCKA(x) ((x)&0x07) |
| 622 | |
| 623 | /* Bit definitions and macros for PWM_CAE */ |
| 624 | #define PWM_CAE_CAE7 (0x80) |
| 625 | #define PWM_CAE_CAE5 (0x20) |
| 626 | #define PWM_CAE_CAE3 (0x08) |
| 627 | #define PWM_CAE_CAE1 (0x02) |
| 628 | |
| 629 | /* Bit definitions and macros for PWM_CTL */ |
| 630 | #define PWM_CTL_CON67 (0x80) |
| 631 | #define PWM_CTL_CON45 (0x40) |
| 632 | #define PWM_CTL_CON23 (0x20) |
| 633 | #define PWM_CTL_CON01 (0x10) |
| 634 | #define PWM_CTL_PSWAR (0x08) |
| 635 | #define PWM_CTL_PFRZ (0x04) |
| 636 | |
| 637 | /* Bit definitions and macros for PWM_SDN */ |
| 638 | #define PWM_SDN_IF (0x80) |
| 639 | #define PWM_SDN_IE (0x40) |
| 640 | #define PWM_SDN_RESTART (0x20) |
| 641 | #define PWM_SDN_LVL (0x10) |
| 642 | #define PWM_SDN_PWM7IN (0x04) |
| 643 | #define PWM_SDN_PWM7IL (0x02) |
| 644 | #define PWM_SDN_SDNEN (0x01) |
| 645 | |
| 646 | /********************************************************************* |
| 647 | * Watchdog Timer Modules (WTM) |
| 648 | *********************************************************************/ |
| 649 | /* Bit definitions and macros for WTM_WCR */ |
| 650 | #define WTM_WCR_WAIT (0x0008) |
| 651 | #define WTM_WCR_DOZE (0x0004) |
| 652 | #define WTM_WCR_HALTED (0x0002) |
| 653 | #define WTM_WCR_EN (0x0001) |
| 654 | |
| 655 | /********************************************************************* |
| 656 | * Chip Configuration Module (CCM) |
| 657 | *********************************************************************/ |
| 658 | /* Bit definitions and macros for CCM_CCR */ |
| 659 | #define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) |
| 660 | #define CCM_CCR_LIMP (0x0041) |
| 661 | #define CCM_CCR_LOAD (0x0021) |
| 662 | #define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) |
| 663 | #define CCM_CCR_OSC_MODE (0x0005) |
| 664 | #define CCM_CCR_PLL_MODE (0x0003) |
| 665 | #define CCM_CCR_RESERVED (0x0001) |
| 666 | |
| 667 | /* Bit definitions and macros for CCM_RCON */ |
| 668 | #define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) |
| 669 | #define CCM_RCON_LIMP (0x0041) |
| 670 | #define CCM_RCON_LOAD (0x0021) |
| 671 | #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) |
| 672 | #define CCM_RCON_OSC_MODE (0x0005) |
| 673 | #define CCM_RCON_PLL_MODE (0x0003) |
| 674 | #define CCM_RCON_RESERVED (0x0001) |
| 675 | |
| 676 | /* Bit definitions and macros for CCM_CIR */ |
| 677 | #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) |
| 678 | #define CCM_CIR_PRN(x) ((x)&0x003F) |
| 679 | |
| 680 | /* Bit definitions and macros for CCM_MISCCR */ |
| 681 | #define CCM_MISCCR_PLL_LOCK (0x2000) |
| 682 | #define CCM_MISCCR_LIMP (0x1000) |
| 683 | #define CCM_MISCCR_LCD_CHEN (0x0100) |
| 684 | #define CCM_MISCCR_SSI_PUE (0x0080) |
| 685 | #define CCM_MISCCR_SSI_PUS (0x0040) |
| 686 | #define CCM_MISCCR_TIM_DMA (0x0020) |
| 687 | #define CCM_MISCCR_SSI_SRC (0x0010) |
| 688 | #define CCM_MISCCR_USBDIV (0x0002) |
| 689 | #define CCM_MISCCR_USBSRC (0x0001) |
| 690 | |
| 691 | /* Bit definitions and macros for CCM_CDR */ |
| 692 | #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) |
| 693 | #define CCM_CDR_SSIDIV(x) ((x)&0x000F) |
| 694 | |
| 695 | /* Bit definitions and macros for CCM_UHCSR */ |
| 696 | #define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) |
| 697 | #define CCM_UHCSR_WKUP (0x0004) |
| 698 | #define CCM_UHCSR_UHMIE (0x0002) |
| 699 | #define CCM_UHCSR_XPDE (0x0001) |
| 700 | |
| 701 | /* Bit definitions and macros for CCM_UOCSR */ |
| 702 | #define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) |
| 703 | #define CCM_UOCSR_DPPD (0x2000) |
| 704 | #define CCM_UOCSR_DMPD (0x1000) |
| 705 | #define CCM_UOCSR_DRV_VBUS (0x0800) |
| 706 | #define CCM_UOCSR_CRG_VBUS (0x0400) |
| 707 | #define CCM_UOCSR_DCR_VBUS (0x0200) |
| 708 | #define CCM_UOCSR_DPPU (0x0100) |
| 709 | #define CCM_UOCSR_AVLD (0x0080) |
| 710 | #define CCM_UOCSR_BVLD (0x0040) |
| 711 | #define CCM_UOCSR_VVLD (0x0020) |
| 712 | #define CCM_UOCSR_SEND (0x0010) |
| 713 | #define CCM_UOCSR_PWRFLT (0x0008) |
| 714 | #define CCM_UOCSR_WKUP (0x0004) |
| 715 | #define CCM_UOCSR_UOMIE (0x0002) |
| 716 | #define CCM_UOCSR_XPDE (0x0001) |
| 717 | |
| 718 | /* not done yet */ |
| 719 | /********************************************************************* |
| 720 | * General Purpose I/O (GPIO) |
| 721 | *********************************************************************/ |
| 722 | /* Bit definitions and macros for GPIO_PODR_FECH_L */ |
| 723 | #define GPIO_PODR_FECH_L7 (0x80) |
| 724 | #define GPIO_PODR_FECH_L6 (0x40) |
| 725 | #define GPIO_PODR_FECH_L5 (0x20) |
| 726 | #define GPIO_PODR_FECH_L4 (0x10) |
| 727 | #define GPIO_PODR_FECH_L3 (0x08) |
| 728 | #define GPIO_PODR_FECH_L2 (0x04) |
| 729 | #define GPIO_PODR_FECH_L1 (0x02) |
| 730 | #define GPIO_PODR_FECH_L0 (0x01) |
| 731 | |
| 732 | /* Bit definitions and macros for GPIO_PODR_SSI */ |
| 733 | #define GPIO_PODR_SSI_4 (0x10) |
| 734 | #define GPIO_PODR_SSI_3 (0x08) |
| 735 | #define GPIO_PODR_SSI_2 (0x04) |
| 736 | #define GPIO_PODR_SSI_1 (0x02) |
| 737 | #define GPIO_PODR_SSI_0 (0x01) |
| 738 | |
| 739 | /* Bit definitions and macros for GPIO_PODR_BUSCTL */ |
| 740 | #define GPIO_PODR_BUSCTL_3 (0x08) |
| 741 | #define GPIO_PODR_BUSCTL_2 (0x04) |
| 742 | #define GPIO_PODR_BUSCTL_1 (0x02) |
| 743 | #define GPIO_PODR_BUSCTL_0 (0x01) |
| 744 | |
| 745 | /* Bit definitions and macros for GPIO_PODR_BE */ |
| 746 | #define GPIO_PODR_BE_3 (0x08) |
| 747 | #define GPIO_PODR_BE_2 (0x04) |
| 748 | #define GPIO_PODR_BE_1 (0x02) |
| 749 | #define GPIO_PODR_BE_0 (0x01) |
| 750 | |
| 751 | /* Bit definitions and macros for GPIO_PODR_CS */ |
| 752 | #define GPIO_PODR_CS_5 (0x20) |
| 753 | #define GPIO_PODR_CS_4 (0x10) |
| 754 | #define GPIO_PODR_CS_3 (0x08) |
| 755 | #define GPIO_PODR_CS_2 (0x04) |
| 756 | #define GPIO_PODR_CS_1 (0x02) |
| 757 | |
| 758 | /* Bit definitions and macros for GPIO_PODR_PWM */ |
| 759 | #define GPIO_PODR_PWM_5 (0x20) |
| 760 | #define GPIO_PODR_PWM_4 (0x10) |
| 761 | #define GPIO_PODR_PWM_3 (0x08) |
| 762 | #define GPIO_PODR_PWM_2 (0x04) |
| 763 | |
| 764 | /* Bit definitions and macros for GPIO_PODR_FECI2C */ |
| 765 | #define GPIO_PODR_FECI2C_3 (0x08) |
| 766 | #define GPIO_PODR_FECI2C_2 (0x04) |
| 767 | #define GPIO_PODR_FECI2C_1 (0x02) |
| 768 | #define GPIO_PODR_FECI2C_0 (0x01) |
| 769 | |
| 770 | /* Bit definitions and macros for GPIO_PODR_UART */ |
| 771 | #define GPIO_PODR_UART_7 (0x80) |
| 772 | #define GPIO_PODR_UART_6 (0x40) |
| 773 | #define GPIO_PODR_UART_5 (0x20) |
| 774 | #define GPIO_PODR_UART_4 (0x10) |
| 775 | #define GPIO_PODR_UART_3 (0x08) |
| 776 | #define GPIO_PODR_UART_2 (0x04) |
| 777 | #define GPIO_PODR_UART_1 (0x02) |
| 778 | #define GPIO_PODR_UART_0 (0x01) |
| 779 | |
| 780 | /* Bit definitions and macros for GPIO_PODR_QSPI */ |
| 781 | #define GPIO_PODR_QSPI_5 (0x20) |
| 782 | #define GPIO_PODR_QSPI_4 (0x10) |
| 783 | #define GPIO_PODR_QSPI_3 (0x08) |
| 784 | #define GPIO_PODR_QSPI_2 (0x04) |
| 785 | #define GPIO_PODR_QSPI_1 (0x02) |
| 786 | #define GPIO_PODR_QSPI_0 (0x01) |
| 787 | |
| 788 | /* Bit definitions and macros for GPIO_PODR_TIMER */ |
| 789 | #define GPIO_PODR_TIMER_3 (0x08) |
| 790 | #define GPIO_PODR_TIMER_2 (0x04) |
| 791 | #define GPIO_PODR_TIMER_1 (0x02) |
| 792 | #define GPIO_PODR_TIMER_0 (0x01) |
| 793 | |
| 794 | /* Bit definitions and macros for GPIO_PODR_LCDDATAH */ |
| 795 | #define GPIO_PODR_LCDDATAH_1 (0x02) |
| 796 | #define GPIO_PODR_LCDDATAH_0 (0x01) |
| 797 | |
| 798 | /* Bit definitions and macros for GPIO_PODR_LCDDATAM */ |
| 799 | #define GPIO_PODR_LCDDATAM_7 (0x80) |
| 800 | #define GPIO_PODR_LCDDATAM_6 (0x40) |
| 801 | #define GPIO_PODR_LCDDATAM_5 (0x20) |
| 802 | #define GPIO_PODR_LCDDATAM_4 (0x10) |
| 803 | #define GPIO_PODR_LCDDATAM_3 (0x08) |
| 804 | #define GPIO_PODR_LCDDATAM_2 (0x04) |
| 805 | #define GPIO_PODR_LCDDATAM_1 (0x02) |
| 806 | #define GPIO_PODR_LCDDATAM_0 (0x01) |
| 807 | |
| 808 | /* Bit definitions and macros for GPIO_PODR_LCDDATAL */ |
| 809 | #define GPIO_PODR_LCDDATAL_7 (0x80) |
| 810 | #define GPIO_PODR_LCDDATAL_6 (0x40) |
| 811 | #define GPIO_PODR_LCDDATAL_5 (0x20) |
| 812 | #define GPIO_PODR_LCDDATAL_4 (0x10) |
| 813 | #define GPIO_PODR_LCDDATAL_3 (0x08) |
| 814 | #define GPIO_PODR_LCDDATAL_2 (0x04) |
| 815 | #define GPIO_PODR_LCDDATAL_1 (0x02) |
| 816 | #define GPIO_PODR_LCDDATAL_0 (0x01) |
| 817 | |
| 818 | /* Bit definitions and macros for GPIO_PODR_LCDCTLH */ |
| 819 | #define GPIO_PODR_LCDCTLH_0 (0x01) |
| 820 | |
| 821 | /* Bit definitions and macros for GPIO_PODR_LCDCTLL */ |
| 822 | #define GPIO_PODR_LCDCTLL_7 (0x80) |
| 823 | #define GPIO_PODR_LCDCTLL_6 (0x40) |
| 824 | #define GPIO_PODR_LCDCTLL_5 (0x20) |
| 825 | #define GPIO_PODR_LCDCTLL_4 (0x10) |
| 826 | #define GPIO_PODR_LCDCTLL_3 (0x08) |
| 827 | #define GPIO_PODR_LCDCTLL_2 (0x04) |
| 828 | #define GPIO_PODR_LCDCTLL_1 (0x02) |
| 829 | #define GPIO_PODR_LCDCTLL_0 (0x01) |
| 830 | |
| 831 | /* Bit definitions and macros for GPIO_PDDR_FECH */ |
| 832 | #define GPIO_PDDR_FECH_L7 (0x80) |
| 833 | #define GPIO_PDDR_FECH_L6 (0x40) |
| 834 | #define GPIO_PDDR_FECH_L5 (0x20) |
| 835 | #define GPIO_PDDR_FECH_L4 (0x10) |
| 836 | #define GPIO_PDDR_FECH_L3 (0x08) |
| 837 | #define GPIO_PDDR_FECH_L2 (0x04) |
| 838 | #define GPIO_PDDR_FECH_L1 (0x02) |
| 839 | #define GPIO_PDDR_FECH_L0 (0x01) |
| 840 | |
| 841 | /* Bit definitions and macros for GPIO_PDDR_SSI */ |
| 842 | #define GPIO_PDDR_SSI_4 (0x10) |
| 843 | #define GPIO_PDDR_SSI_3 (0x08) |
| 844 | #define GPIO_PDDR_SSI_2 (0x04) |
| 845 | #define GPIO_PDDR_SSI_1 (0x02) |
| 846 | #define GPIO_PDDR_SSI_0 (0x01) |
| 847 | |
| 848 | /* Bit definitions and macros for GPIO_PDDR_BUSCTL */ |
| 849 | #define GPIO_PDDR_BUSCTL_3 (0x08) |
| 850 | #define GPIO_PDDR_BUSCTL_2 (0x04) |
| 851 | #define GPIO_PDDR_BUSCTL_1 (0x02) |
| 852 | #define GPIO_PDDR_BUSCTL_0 (0x01) |
| 853 | |
| 854 | /* Bit definitions and macros for GPIO_PDDR_BE */ |
| 855 | #define GPIO_PDDR_BE_3 (0x08) |
| 856 | #define GPIO_PDDR_BE_2 (0x04) |
| 857 | #define GPIO_PDDR_BE_1 (0x02) |
| 858 | #define GPIO_PDDR_BE_0 (0x01) |
| 859 | |
| 860 | /* Bit definitions and macros for GPIO_PDDR_CS */ |
| 861 | #define GPIO_PDDR_CS_1 (0x02) |
| 862 | #define GPIO_PDDR_CS_2 (0x04) |
| 863 | #define GPIO_PDDR_CS_3 (0x08) |
| 864 | #define GPIO_PDDR_CS_4 (0x10) |
| 865 | #define GPIO_PDDR_CS_5 (0x20) |
| 866 | |
| 867 | /* Bit definitions and macros for GPIO_PDDR_PWM */ |
| 868 | #define GPIO_PDDR_PWM_2 (0x04) |
| 869 | #define GPIO_PDDR_PWM_3 (0x08) |
| 870 | #define GPIO_PDDR_PWM_4 (0x10) |
| 871 | #define GPIO_PDDR_PWM_5 (0x20) |
| 872 | |
| 873 | /* Bit definitions and macros for GPIO_PDDR_FECI2C */ |
| 874 | #define GPIO_PDDR_FECI2C_0 (0x01) |
| 875 | #define GPIO_PDDR_FECI2C_1 (0x02) |
| 876 | #define GPIO_PDDR_FECI2C_2 (0x04) |
| 877 | #define GPIO_PDDR_FECI2C_3 (0x08) |
| 878 | |
| 879 | /* Bit definitions and macros for GPIO_PDDR_UART */ |
| 880 | #define GPIO_PDDR_UART_0 (0x01) |
| 881 | #define GPIO_PDDR_UART_1 (0x02) |
| 882 | #define GPIO_PDDR_UART_2 (0x04) |
| 883 | #define GPIO_PDDR_UART_3 (0x08) |
| 884 | #define GPIO_PDDR_UART_4 (0x10) |
| 885 | #define GPIO_PDDR_UART_5 (0x20) |
| 886 | #define GPIO_PDDR_UART_6 (0x40) |
| 887 | #define GPIO_PDDR_UART_7 (0x80) |
| 888 | |
| 889 | /* Bit definitions and macros for GPIO_PDDR_QSPI */ |
| 890 | #define GPIO_PDDR_QSPI_0 (0x01) |
| 891 | #define GPIO_PDDR_QSPI_1 (0x02) |
| 892 | #define GPIO_PDDR_QSPI_2 (0x04) |
| 893 | #define GPIO_PDDR_QSPI_3 (0x08) |
| 894 | #define GPIO_PDDR_QSPI_4 (0x10) |
| 895 | #define GPIO_PDDR_QSPI_5 (0x20) |
| 896 | |
| 897 | /* Bit definitions and macros for GPIO_PDDR_TIMER */ |
| 898 | #define GPIO_PDDR_TIMER_0 (0x01) |
| 899 | #define GPIO_PDDR_TIMER_1 (0x02) |
| 900 | #define GPIO_PDDR_TIMER_2 (0x04) |
| 901 | #define GPIO_PDDR_TIMER_3 (0x08) |
| 902 | |
| 903 | /* Bit definitions and macros for GPIO_PDDR_LCDDATAH */ |
| 904 | #define GPIO_PDDR_LCDDATAH_0 (0x01) |
| 905 | #define GPIO_PDDR_LCDDATAH_1 (0x02) |
| 906 | |
| 907 | /* Bit definitions and macros for GPIO_PDDR_LCDDATAM */ |
| 908 | #define GPIO_PDDR_LCDDATAM_0 (0x01) |
| 909 | #define GPIO_PDDR_LCDDATAM_1 (0x02) |
| 910 | #define GPIO_PDDR_LCDDATAM_2 (0x04) |
| 911 | #define GPIO_PDDR_LCDDATAM_3 (0x08) |
| 912 | #define GPIO_PDDR_LCDDATAM_4 (0x10) |
| 913 | #define GPIO_PDDR_LCDDATAM_5 (0x20) |
| 914 | #define GPIO_PDDR_LCDDATAM_6 (0x40) |
| 915 | #define GPIO_PDDR_LCDDATAM_7 (0x80) |
| 916 | |
| 917 | /* Bit definitions and macros for GPIO_PDDR_LCDDATAL */ |
| 918 | #define GPIO_PDDR_LCDDATAL_0 (0x01) |
| 919 | #define GPIO_PDDR_LCDDATAL_1 (0x02) |
| 920 | #define GPIO_PDDR_LCDDATAL_2 (0x04) |
| 921 | #define GPIO_PDDR_LCDDATAL_3 (0x08) |
| 922 | #define GPIO_PDDR_LCDDATAL_4 (0x10) |
| 923 | #define GPIO_PDDR_LCDDATAL_5 (0x20) |
| 924 | #define GPIO_PDDR_LCDDATAL_6 (0x40) |
| 925 | #define GPIO_PDDR_LCDDATAL_7 (0x80) |
| 926 | |
| 927 | /* Bit definitions and macros for GPIO_PDDR_LCDCTLH */ |
| 928 | #define GPIO_PDDR_LCDCTLH_0 (0x01) |
| 929 | |
| 930 | /* Bit definitions and macros for GPIO_PDDR_LCDCTLL */ |
| 931 | #define GPIO_PDDR_LCDCTLL_0 (0x01) |
| 932 | #define GPIO_PDDR_LCDCTLL_1 (0x02) |
| 933 | #define GPIO_PDDR_LCDCTLL_2 (0x04) |
| 934 | #define GPIO_PDDR_LCDCTLL_3 (0x08) |
| 935 | #define GPIO_PDDR_LCDCTLL_4 (0x10) |
| 936 | #define GPIO_PDDR_LCDCTLL_5 (0x20) |
| 937 | #define GPIO_PDDR_LCDCTLL_6 (0x40) |
| 938 | #define GPIO_PDDR_LCDCTLL_7 (0x80) |
| 939 | |
| 940 | /* Bit definitions and macros for GPIO_PPDSDR_FECH */ |
| 941 | #define GPIO_PPDSDR_FECH_L0 (0x01) |
| 942 | #define GPIO_PPDSDR_FECH_L1 (0x02) |
| 943 | #define GPIO_PPDSDR_FECH_L2 (0x04) |
| 944 | #define GPIO_PPDSDR_FECH_L3 (0x08) |
| 945 | #define GPIO_PPDSDR_FECH_L4 (0x10) |
| 946 | #define GPIO_PPDSDR_FECH_L5 (0x20) |
| 947 | #define GPIO_PPDSDR_FECH_L6 (0x40) |
| 948 | #define GPIO_PPDSDR_FECH_L7 (0x80) |
| 949 | |
| 950 | /* Bit definitions and macros for GPIO_PPDSDR_SSI */ |
| 951 | #define GPIO_PPDSDR_SSI_0 (0x01) |
| 952 | #define GPIO_PPDSDR_SSI_1 (0x02) |
| 953 | #define GPIO_PPDSDR_SSI_2 (0x04) |
| 954 | #define GPIO_PPDSDR_SSI_3 (0x08) |
| 955 | #define GPIO_PPDSDR_SSI_4 (0x10) |
| 956 | |
| 957 | /* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */ |
| 958 | #define GPIO_PPDSDR_BUSCTL_0 (0x01) |
| 959 | #define GPIO_PPDSDR_BUSCTL_1 (0x02) |
| 960 | #define GPIO_PPDSDR_BUSCTL_2 (0x04) |
| 961 | #define GPIO_PPDSDR_BUSCTL_3 (0x08) |
| 962 | |
| 963 | /* Bit definitions and macros for GPIO_PPDSDR_BE */ |
| 964 | #define GPIO_PPDSDR_BE_0 (0x01) |
| 965 | #define GPIO_PPDSDR_BE_1 (0x02) |
| 966 | #define GPIO_PPDSDR_BE_2 (0x04) |
| 967 | #define GPIO_PPDSDR_BE_3 (0x08) |
| 968 | |
| 969 | /* Bit definitions and macros for GPIO_PPDSDR_CS */ |
| 970 | #define GPIO_PPDSDR_CS_1 (0x02) |
| 971 | #define GPIO_PPDSDR_CS_2 (0x04) |
| 972 | #define GPIO_PPDSDR_CS_3 (0x08) |
| 973 | #define GPIO_PPDSDR_CS_4 (0x10) |
| 974 | #define GPIO_PPDSDR_CS_5 (0x20) |
| 975 | |
| 976 | /* Bit definitions and macros for GPIO_PPDSDR_PWM */ |
| 977 | #define GPIO_PPDSDR_PWM_2 (0x04) |
| 978 | #define GPIO_PPDSDR_PWM_3 (0x08) |
| 979 | #define GPIO_PPDSDR_PWM_4 (0x10) |
| 980 | #define GPIO_PPDSDR_PWM_5 (0x20) |
| 981 | |
| 982 | /* Bit definitions and macros for GPIO_PPDSDR_FECI2C */ |
| 983 | #define GPIO_PPDSDR_FECI2C_0 (0x01) |
| 984 | #define GPIO_PPDSDR_FECI2C_1 (0x02) |
| 985 | #define GPIO_PPDSDR_FECI2C_2 (0x04) |
| 986 | #define GPIO_PPDSDR_FECI2C_3 (0x08) |
| 987 | |
| 988 | /* Bit definitions and macros for GPIO_PPDSDR_UART */ |
| 989 | #define GPIO_PPDSDR_UART_0 (0x01) |
| 990 | #define GPIO_PPDSDR_UART_1 (0x02) |
| 991 | #define GPIO_PPDSDR_UART_2 (0x04) |
| 992 | #define GPIO_PPDSDR_UART_3 (0x08) |
| 993 | #define GPIO_PPDSDR_UART_4 (0x10) |
| 994 | #define GPIO_PPDSDR_UART_5 (0x20) |
| 995 | #define GPIO_PPDSDR_UART_6 (0x40) |
| 996 | #define GPIO_PPDSDR_UART_7 (0x80) |
| 997 | |
| 998 | /* Bit definitions and macros for GPIO_PPDSDR_QSPI */ |
| 999 | #define GPIO_PPDSDR_QSPI_0 (0x01) |
| 1000 | #define GPIO_PPDSDR_QSPI_1 (0x02) |
| 1001 | #define GPIO_PPDSDR_QSPI_2 (0x04) |
| 1002 | #define GPIO_PPDSDR_QSPI_3 (0x08) |
| 1003 | #define GPIO_PPDSDR_QSPI_4 (0x10) |
| 1004 | #define GPIO_PPDSDR_QSPI_5 (0x20) |
| 1005 | |
| 1006 | /* Bit definitions and macros for GPIO_PPDSDR_TIMER */ |
| 1007 | #define GPIO_PPDSDR_TIMER_0 (0x01) |
| 1008 | #define GPIO_PPDSDR_TIMER_1 (0x02) |
| 1009 | #define GPIO_PPDSDR_TIMER_2 (0x04) |
| 1010 | #define GPIO_PPDSDR_TIMER_3 (0x08) |
| 1011 | |
| 1012 | /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */ |
| 1013 | #define GPIO_PPDSDR_LCDDATAH_0 (0x01) |
| 1014 | #define GPIO_PPDSDR_LCDDATAH_1 (0x02) |
| 1015 | |
| 1016 | /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */ |
| 1017 | #define GPIO_PPDSDR_LCDDATAM_0 (0x01) |
| 1018 | #define GPIO_PPDSDR_LCDDATAM_1 (0x02) |
| 1019 | #define GPIO_PPDSDR_LCDDATAM_2 (0x04) |
| 1020 | #define GPIO_PPDSDR_LCDDATAM_3 (0x08) |
| 1021 | #define GPIO_PPDSDR_LCDDATAM_4 (0x10) |
| 1022 | #define GPIO_PPDSDR_LCDDATAM_5 (0x20) |
| 1023 | #define GPIO_PPDSDR_LCDDATAM_6 (0x40) |
| 1024 | #define GPIO_PPDSDR_LCDDATAM_7 (0x80) |
| 1025 | |
| 1026 | /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */ |
| 1027 | #define GPIO_PPDSDR_LCDDATAL_0 (0x01) |
| 1028 | #define GPIO_PPDSDR_LCDDATAL_1 (0x02) |
| 1029 | #define GPIO_PPDSDR_LCDDATAL_2 (0x04) |
| 1030 | #define GPIO_PPDSDR_LCDDATAL_3 (0x08) |
| 1031 | #define GPIO_PPDSDR_LCDDATAL_4 (0x10) |
| 1032 | #define GPIO_PPDSDR_LCDDATAL_5 (0x20) |
| 1033 | #define GPIO_PPDSDR_LCDDATAL_6 (0x40) |
| 1034 | #define GPIO_PPDSDR_LCDDATAL_7 (0x80) |
| 1035 | |
| 1036 | /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */ |
| 1037 | #define GPIO_PPDSDR_LCDCTLH_0 (0x01) |
| 1038 | |
| 1039 | /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */ |
| 1040 | #define GPIO_PPDSDR_LCDCTLL_0 (0x01) |
| 1041 | #define GPIO_PPDSDR_LCDCTLL_1 (0x02) |
| 1042 | #define GPIO_PPDSDR_LCDCTLL_2 (0x04) |
| 1043 | #define GPIO_PPDSDR_LCDCTLL_3 (0x08) |
| 1044 | #define GPIO_PPDSDR_LCDCTLL_4 (0x10) |
| 1045 | #define GPIO_PPDSDR_LCDCTLL_5 (0x20) |
| 1046 | #define GPIO_PPDSDR_LCDCTLL_6 (0x40) |
| 1047 | #define GPIO_PPDSDR_LCDCTLL_7 (0x80) |
| 1048 | |
| 1049 | /* Bit definitions and macros for GPIO_PCLRR_FECH */ |
| 1050 | #define GPIO_PCLRR_FECH_L0 (0x01) |
| 1051 | #define GPIO_PCLRR_FECH_L1 (0x02) |
| 1052 | #define GPIO_PCLRR_FECH_L2 (0x04) |
| 1053 | #define GPIO_PCLRR_FECH_L3 (0x08) |
| 1054 | #define GPIO_PCLRR_FECH_L4 (0x10) |
| 1055 | #define GPIO_PCLRR_FECH_L5 (0x20) |
| 1056 | #define GPIO_PCLRR_FECH_L6 (0x40) |
| 1057 | #define GPIO_PCLRR_FECH_L7 (0x80) |
| 1058 | |
| 1059 | /* Bit definitions and macros for GPIO_PCLRR_SSI */ |
| 1060 | #define GPIO_PCLRR_SSI_0 (0x01) |
| 1061 | #define GPIO_PCLRR_SSI_1 (0x02) |
| 1062 | #define GPIO_PCLRR_SSI_2 (0x04) |
| 1063 | #define GPIO_PCLRR_SSI_3 (0x08) |
| 1064 | #define GPIO_PCLRR_SSI_4 (0x10) |
| 1065 | |
| 1066 | /* Bit definitions and macros for GPIO_PCLRR_BUSCTL */ |
| 1067 | #define GPIO_PCLRR_BUSCTL_L0 (0x01) |
| 1068 | #define GPIO_PCLRR_BUSCTL_L1 (0x02) |
| 1069 | #define GPIO_PCLRR_BUSCTL_L2 (0x04) |
| 1070 | #define GPIO_PCLRR_BUSCTL_L3 (0x08) |
| 1071 | |
| 1072 | /* Bit definitions and macros for GPIO_PCLRR_BE */ |
| 1073 | #define GPIO_PCLRR_BE_0 (0x01) |
| 1074 | #define GPIO_PCLRR_BE_1 (0x02) |
| 1075 | #define GPIO_PCLRR_BE_2 (0x04) |
| 1076 | #define GPIO_PCLRR_BE_3 (0x08) |
| 1077 | |
| 1078 | /* Bit definitions and macros for GPIO_PCLRR_CS */ |
| 1079 | #define GPIO_PCLRR_CS_1 (0x02) |
| 1080 | #define GPIO_PCLRR_CS_2 (0x04) |
| 1081 | #define GPIO_PCLRR_CS_3 (0x08) |
| 1082 | #define GPIO_PCLRR_CS_4 (0x10) |
| 1083 | #define GPIO_PCLRR_CS_5 (0x20) |
| 1084 | |
| 1085 | /* Bit definitions and macros for GPIO_PCLRR_PWM */ |
| 1086 | #define GPIO_PCLRR_PWM_2 (0x04) |
| 1087 | #define GPIO_PCLRR_PWM_3 (0x08) |
| 1088 | #define GPIO_PCLRR_PWM_4 (0x10) |
| 1089 | #define GPIO_PCLRR_PWM_5 (0x20) |
| 1090 | |
| 1091 | /* Bit definitions and macros for GPIO_PCLRR_FECI2C */ |
| 1092 | #define GPIO_PCLRR_FECI2C_0 (0x01) |
| 1093 | #define GPIO_PCLRR_FECI2C_1 (0x02) |
| 1094 | #define GPIO_PCLRR_FECI2C_2 (0x04) |
| 1095 | #define GPIO_PCLRR_FECI2C_3 (0x08) |
| 1096 | |
| 1097 | /* Bit definitions and macros for GPIO_PCLRR_UART */ |
| 1098 | #define GPIO_PCLRR_UART0 (0x01) |
| 1099 | #define GPIO_PCLRR_UART1 (0x02) |
| 1100 | #define GPIO_PCLRR_UART2 (0x04) |
| 1101 | #define GPIO_PCLRR_UART3 (0x08) |
| 1102 | #define GPIO_PCLRR_UART4 (0x10) |
| 1103 | #define GPIO_PCLRR_UART5 (0x20) |
| 1104 | #define GPIO_PCLRR_UART6 (0x40) |
| 1105 | #define GPIO_PCLRR_UART7 (0x80) |
| 1106 | |
| 1107 | /* Bit definitions and macros for GPIO_PCLRR_QSPI */ |
| 1108 | #define GPIO_PCLRR_QSPI0 (0x01) |
| 1109 | #define GPIO_PCLRR_QSPI1 (0x02) |
| 1110 | #define GPIO_PCLRR_QSPI2 (0x04) |
| 1111 | #define GPIO_PCLRR_QSPI3 (0x08) |
| 1112 | #define GPIO_PCLRR_QSPI4 (0x10) |
| 1113 | #define GPIO_PCLRR_QSPI5 (0x20) |
| 1114 | |
| 1115 | /* Bit definitions and macros for GPIO_PCLRR_TIMER */ |
| 1116 | #define GPIO_PCLRR_TIMER0 (0x01) |
| 1117 | #define GPIO_PCLRR_TIMER1 (0x02) |
| 1118 | #define GPIO_PCLRR_TIMER2 (0x04) |
| 1119 | #define GPIO_PCLRR_TIMER3 (0x08) |
| 1120 | |
| 1121 | /* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */ |
| 1122 | #define GPIO_PCLRR_LCDDATAH0 (0x01) |
| 1123 | #define GPIO_PCLRR_LCDDATAH1 (0x02) |
| 1124 | |
| 1125 | /* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */ |
| 1126 | #define GPIO_PCLRR_LCDDATAM0 (0x01) |
| 1127 | #define GPIO_PCLRR_LCDDATAM1 (0x02) |
| 1128 | #define GPIO_PCLRR_LCDDATAM2 (0x04) |
| 1129 | #define GPIO_PCLRR_LCDDATAM3 (0x08) |
| 1130 | #define GPIO_PCLRR_LCDDATAM4 (0x10) |
| 1131 | #define GPIO_PCLRR_LCDDATAM5 (0x20) |
| 1132 | #define GPIO_PCLRR_LCDDATAM6 (0x40) |
| 1133 | #define GPIO_PCLRR_LCDDATAM7 (0x80) |
| 1134 | |
| 1135 | /* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */ |
| 1136 | #define GPIO_PCLRR_LCDDATAL0 (0x01) |
| 1137 | #define GPIO_PCLRR_LCDDATAL1 (0x02) |
| 1138 | #define GPIO_PCLRR_LCDDATAL2 (0x04) |
| 1139 | #define GPIO_PCLRR_LCDDATAL3 (0x08) |
| 1140 | #define GPIO_PCLRR_LCDDATAL4 (0x10) |
| 1141 | #define GPIO_PCLRR_LCDDATAL5 (0x20) |
| 1142 | #define GPIO_PCLRR_LCDDATAL6 (0x40) |
| 1143 | #define GPIO_PCLRR_LCDDATAL7 (0x80) |
| 1144 | |
| 1145 | /* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */ |
| 1146 | #define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) |
| 1147 | |
| 1148 | /* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */ |
| 1149 | #define GPIO_PCLRR_LCDCTLL0 (0x01) |
| 1150 | #define GPIO_PCLRR_LCDCTLL1 (0x02) |
| 1151 | #define GPIO_PCLRR_LCDCTLL2 (0x04) |
| 1152 | #define GPIO_PCLRR_LCDCTLL3 (0x08) |
| 1153 | #define GPIO_PCLRR_LCDCTLL4 (0x10) |
| 1154 | #define GPIO_PCLRR_LCDCTLL5 (0x20) |
| 1155 | #define GPIO_PCLRR_LCDCTLL6 (0x40) |
| 1156 | #define GPIO_PCLRR_LCDCTLL7 (0x80) |
| 1157 | |
| 1158 | /* Bit definitions and macros for GPIO_PAR_FEC */ |
| 1159 | #define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) |
| 1160 | #define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) |
| 1161 | #define GPIO_PAR_FEC_7W_GPIO (0x00) |
| 1162 | #define GPIO_PAR_FEC_7W_URTS1 (0x04) |
| 1163 | #define GPIO_PAR_FEC_7W_FEC (0x0C) |
| 1164 | #define GPIO_PAR_FEC_MII_GPIO (0x00) |
| 1165 | #define GPIO_PAR_FEC_MII_UART (0x01) |
| 1166 | #define GPIO_PAR_FEC_MII_FEC (0x03) |
| 1167 | |
| 1168 | /* Bit definitions and macros for GPIO_PAR_PWM */ |
| 1169 | #define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) |
| 1170 | #define GPIO_PAR_PWM3(x) (((x)&0x03)<<2) |
| 1171 | #define GPIO_PAR_PWM5 (0x10) |
| 1172 | #define GPIO_PAR_PWM7 (0x20) |
| 1173 | |
| 1174 | /* Bit definitions and macros for GPIO_PAR_BUSCTL */ |
| 1175 | #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3) |
| 1176 | #define GPIO_PAR_BUSCTL_RWB (0x20) |
| 1177 | #define GPIO_PAR_BUSCTL_TA (0x40) |
| 1178 | #define GPIO_PAR_BUSCTL_OE (0x80) |
| 1179 | #define GPIO_PAR_BUSCTL_OE_GPIO (0x00) |
| 1180 | #define GPIO_PAR_BUSCTL_OE_OE (0x80) |
| 1181 | #define GPIO_PAR_BUSCTL_TA_GPIO (0x00) |
| 1182 | #define GPIO_PAR_BUSCTL_TA_TA (0x40) |
| 1183 | #define GPIO_PAR_BUSCTL_RWB_GPIO (0x00) |
| 1184 | #define GPIO_PAR_BUSCTL_RWB_RWB (0x20) |
| 1185 | #define GPIO_PAR_BUSCTL_TS_GPIO (0x00) |
| 1186 | #define GPIO_PAR_BUSCTL_TS_DACK0 (0x10) |
| 1187 | #define GPIO_PAR_BUSCTL_TS_TS (0x18) |
| 1188 | |
| 1189 | /* Bit definitions and macros for GPIO_PAR_FECI2C */ |
| 1190 | #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0) |
| 1191 | #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) |
| 1192 | #define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4) |
| 1193 | #define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6) |
| 1194 | #define GPIO_PAR_FECI2C_MDC_GPIO (0x00) |
| 1195 | #define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40) |
| 1196 | #define GPIO_PAR_FECI2C_MDC_SCL (0x80) |
| 1197 | #define GPIO_PAR_FECI2C_MDC_EMDC (0xC0) |
| 1198 | #define GPIO_PAR_FECI2C_MDIO_GPIO (0x00) |
| 1199 | #define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10) |
| 1200 | #define GPIO_PAR_FECI2C_MDIO_SDA (0x20) |
| 1201 | #define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30) |
| 1202 | #define GPIO_PAR_FECI2C_SCL_GPIO (0x00) |
| 1203 | #define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04) |
| 1204 | #define GPIO_PAR_FECI2C_SCL_SCL (0x0C) |
| 1205 | #define GPIO_PAR_FECI2C_SDA_GPIO (0x00) |
| 1206 | #define GPIO_PAR_FECI2C_SDA_URXD2 (0x02) |
| 1207 | #define GPIO_PAR_FECI2C_SDA_SDA (0x03) |
| 1208 | |
| 1209 | /* Bit definitions and macros for GPIO_PAR_BE */ |
| 1210 | #define GPIO_PAR_BE0 (0x01) |
| 1211 | #define GPIO_PAR_BE1 (0x02) |
| 1212 | #define GPIO_PAR_BE2 (0x04) |
| 1213 | #define GPIO_PAR_BE3 (0x08) |
| 1214 | |
| 1215 | /* Bit definitions and macros for GPIO_PAR_CS */ |
| 1216 | #define GPIO_PAR_CS1 (0x02) |
| 1217 | #define GPIO_PAR_CS2 (0x04) |
| 1218 | #define GPIO_PAR_CS3 (0x08) |
| 1219 | #define GPIO_PAR_CS4 (0x10) |
| 1220 | #define GPIO_PAR_CS5 (0x20) |
| 1221 | #define GPIO_PAR_CS1_GPIO (0x00) |
| 1222 | #define GPIO_PAR_CS1_SDCS1 (0x01) |
| 1223 | #define GPIO_PAR_CS1_CS1 (0x03) |
| 1224 | |
| 1225 | /* Bit definitions and macros for GPIO_PAR_SSI */ |
| 1226 | #define GPIO_PAR_SSI_MCLK (0x0080) |
| 1227 | #define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8) |
| 1228 | #define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10) |
| 1229 | #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12) |
| 1230 | #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14) |
| 1231 | |
| 1232 | /* Bit definitions and macros for GPIO_PAR_UART */ |
| 1233 | #define GPIO_PAR_UART_TXD0 (0x0001) |
| 1234 | #define GPIO_PAR_UART_RXD0 (0x0002) |
| 1235 | #define GPIO_PAR_UART_RTS0 (0x0004) |
| 1236 | #define GPIO_PAR_UART_CTS0 (0x0008) |
| 1237 | #define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4) |
| 1238 | #define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6) |
| 1239 | #define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8) |
| 1240 | #define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10) |
| 1241 | #define GPIO_PAR_UART_CTS1_GPIO (0x0000) |
| 1242 | #define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800) |
| 1243 | #define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400) |
| 1244 | #define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00) |
| 1245 | #define GPIO_PAR_UART_RTS1_GPIO (0x0000) |
| 1246 | #define GPIO_PAR_UART_RTS1_SSI_FS (0x0200) |
| 1247 | #define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100) |
| 1248 | #define GPIO_PAR_UART_RTS1_URTS1 (0x0300) |
| 1249 | #define GPIO_PAR_UART_RXD1_GPIO (0x0000) |
| 1250 | #define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080) |
| 1251 | #define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040) |
| 1252 | #define GPIO_PAR_UART_RXD1_URXD1 (0x00C0) |
| 1253 | #define GPIO_PAR_UART_TXD1_GPIO (0x0000) |
| 1254 | #define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020) |
| 1255 | #define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010) |
| 1256 | #define GPIO_PAR_UART_TXD1_UTXD1 (0x0030) |
| 1257 | |
| 1258 | /* Bit definitions and macros for GPIO_PAR_QSPI */ |
| 1259 | #define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4) |
| 1260 | #define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6) |
| 1261 | #define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8) |
| 1262 | #define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10) |
| 1263 | #define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12) |
| 1264 | #define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14) |
| 1265 | |
| 1266 | /* Bit definitions and macros for GPIO_PAR_TIMER */ |
| 1267 | #define GPIO_PAR_TIN0(x) (((x)&0x03)<<0) |
| 1268 | #define GPIO_PAR_TIN1(x) (((x)&0x03)<<2) |
| 1269 | #define GPIO_PAR_TIN2(x) (((x)&0x03)<<4) |
| 1270 | #define GPIO_PAR_TIN3(x) (((x)&0x03)<<6) |
| 1271 | #define GPIO_PAR_TIN3_GPIO (0x00) |
| 1272 | #define GPIO_PAR_TIN3_TOUT3 (0x80) |
| 1273 | #define GPIO_PAR_TIN3_URXD2 (0x40) |
| 1274 | #define GPIO_PAR_TIN3_TIN3 (0xC0) |
| 1275 | #define GPIO_PAR_TIN2_GPIO (0x00) |
| 1276 | #define GPIO_PAR_TIN2_TOUT2 (0x20) |
| 1277 | #define GPIO_PAR_TIN2_UTXD2 (0x10) |
| 1278 | #define GPIO_PAR_TIN2_TIN2 (0x30) |
| 1279 | #define GPIO_PAR_TIN1_GPIO (0x00) |
| 1280 | #define GPIO_PAR_TIN1_TOUT1 (0x08) |
| 1281 | #define GPIO_PAR_TIN1_DACK1 (0x04) |
| 1282 | #define GPIO_PAR_TIN1_TIN1 (0x0C) |
| 1283 | #define GPIO_PAR_TIN0_GPIO (0x00) |
| 1284 | #define GPIO_PAR_TIN0_TOUT0 (0x02) |
| 1285 | #define GPIO_PAR_TIN0_DREQ0 (0x01) |
| 1286 | #define GPIO_PAR_TIN0_TIN0 (0x03) |
| 1287 | |
| 1288 | /* Bit definitions and macros for GPIO_PAR_LCDDATA */ |
| 1289 | #define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03) |
| 1290 | #define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2) |
| 1291 | #define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4) |
| 1292 | #define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6) |
| 1293 | |
| 1294 | /* Bit definitions and macros for GPIO_PAR_LCDCTL */ |
| 1295 | #define GPIO_PAR_LCDCTL_CLS (0x0001) |
| 1296 | #define GPIO_PAR_LCDCTL_PS (0x0002) |
| 1297 | #define GPIO_PAR_LCDCTL_REV (0x0004) |
| 1298 | #define GPIO_PAR_LCDCTL_SPL_SPR (0x0008) |
| 1299 | #define GPIO_PAR_LCDCTL_CONTRAST (0x0010) |
| 1300 | #define GPIO_PAR_LCDCTL_LSCLK (0x0020) |
| 1301 | #define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040) |
| 1302 | #define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080) |
| 1303 | #define GPIO_PAR_LCDCTL_ACD_OE (0x0100) |
| 1304 | |
| 1305 | /* Bit definitions and macros for GPIO_PAR_IRQ */ |
| 1306 | #define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4) |
| 1307 | #define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6) |
| 1308 | #define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8) |
| 1309 | #define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10) |
| 1310 | #define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12) |
| 1311 | |
| 1312 | /* Bit definitions and macros for GPIO_MSCR_FLEXBUS */ |
| 1313 | #define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03) |
| 1314 | #define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2) |
| 1315 | #define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4) |
| 1316 | |
| 1317 | /* Bit definitions and macros for GPIO_MSCR_SDRAM */ |
| 1318 | #define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03) |
| 1319 | #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) |
| 1320 | #define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4) |
| 1321 | |
| 1322 | /* Bit definitions and macros for GPIO_DSCR_I2C */ |
| 1323 | #define GPIO_DSCR_I2C_DSE(x) ((x)&0x03) |
| 1324 | |
| 1325 | /* Bit definitions and macros for GPIO_DSCR_PWM */ |
| 1326 | #define GPIO_DSCR_PWM_DSE(x) ((x)&0x03) |
| 1327 | |
| 1328 | /* Bit definitions and macros for GPIO_DSCR_FEC */ |
| 1329 | #define GPIO_DSCR_FEC_DSE(x) ((x)&0x03) |
| 1330 | |
| 1331 | /* Bit definitions and macros for GPIO_DSCR_UART */ |
| 1332 | #define GPIO_DSCR_UART0_DSE(x) ((x)&0x03) |
| 1333 | #define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2) |
| 1334 | |
| 1335 | /* Bit definitions and macros for GPIO_DSCR_QSPI */ |
| 1336 | #define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03) |
| 1337 | |
| 1338 | /* Bit definitions and macros for GPIO_DSCR_TIMER */ |
| 1339 | #define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03) |
| 1340 | |
| 1341 | /* Bit definitions and macros for GPIO_DSCR_SSI */ |
| 1342 | #define GPIO_DSCR_SSI_DSE(x) ((x)&0x03) |
| 1343 | |
| 1344 | /* Bit definitions and macros for GPIO_DSCR_LCD */ |
| 1345 | #define GPIO_DSCR_LCD_DSE(x) ((x)&0x03) |
| 1346 | |
| 1347 | /* Bit definitions and macros for GPIO_DSCR_DEBUG */ |
| 1348 | #define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03) |
| 1349 | |
| 1350 | /* Bit definitions and macros for GPIO_DSCR_CLKRST */ |
| 1351 | #define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03) |
| 1352 | |
| 1353 | /* Bit definitions and macros for GPIO_DSCR_IRQ */ |
| 1354 | #define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03) |
| 1355 | |
| 1356 | /* not done yet */ |
| 1357 | /********************************************************************* |
| 1358 | * LCD Controller (LCDC) |
| 1359 | *********************************************************************/ |
| 1360 | /* Bit definitions and macros for LCDC_LSSAR */ |
| 1361 | #define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) |
| 1362 | |
| 1363 | /* Bit definitions and macros for LCDC_LSR */ |
| 1364 | #define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) |
| 1365 | #define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) |
| 1366 | |
| 1367 | /* Bit definitions and macros for LCDC_LVPWR */ |
| 1368 | #define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) |
| 1369 | |
| 1370 | /* Bit definitions and macros for LCDC_LCPR */ |
| 1371 | #define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) |
| 1372 | #define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) |
| 1373 | #define LCDC_LCPR_OP (0x10000000) |
| 1374 | #define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) |
| 1375 | #define LCDC_LCPR_CC_TRANSPARENT (0x00000000) |
| 1376 | #define LCDC_LCPR_CC_OR (0x40000000) |
| 1377 | #define LCDC_LCPR_CC_XOR (0x80000000) |
| 1378 | #define LCDC_LCPR_CC_AND (0xC0000000) |
| 1379 | #define LCDC_LCPR_OP_ON (0x10000000) |
| 1380 | #define LCDC_LCPR_OP_OFF (0x00000000) |
| 1381 | |
| 1382 | /* Bit definitions and macros for LCDC_LCWHBR */ |
| 1383 | #define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) |
| 1384 | #define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) |
| 1385 | #define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) |
| 1386 | #define LCDC_LCWHBR_BK_EN (0x80000000) |
| 1387 | #define LCDC_LCWHBR_BK_EN_ON (0x80000000) |
| 1388 | #define LCDC_LCWHBR_BK_EN_OFF (0x00000000) |
| 1389 | |
| 1390 | /* Bit definitions and macros for LCDC_LCCMR */ |
| 1391 | #define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) |
| 1392 | #define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) |
| 1393 | #define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) |
| 1394 | |
| 1395 | /* Bit definitions and macros for LCDC_LPCR */ |
| 1396 | #define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) |
| 1397 | #define LCDC_LPCR_SHARP (0x00000040) |
| 1398 | #define LCDC_LPCR_SCLKSEL (0x00000080) |
| 1399 | #define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) |
| 1400 | #define LCDC_LPCR_ACDSEL (0x00008000) |
| 1401 | #define LCDC_LPCR_REV_VS (0x00010000) |
| 1402 | #define LCDC_LPCR_SWAP_SEL (0x00020000) |
| 1403 | #define LCDC_LPCR_ENDSEL (0x00040000) |
| 1404 | #define LCDC_LPCR_SCLKIDLE (0x00080000) |
| 1405 | #define LCDC_LPCR_OEPOL (0x00100000) |
| 1406 | #define LCDC_LPCR_CLKPOL (0x00200000) |
| 1407 | #define LCDC_LPCR_LPPOL (0x00400000) |
| 1408 | #define LCDC_LPCR_FLM (0x00800000) |
| 1409 | #define LCDC_LPCR_PIXPOL (0x01000000) |
| 1410 | #define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) |
| 1411 | #define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) |
| 1412 | #define LCDC_LPCR_COLOR (0x40000000) |
| 1413 | #define LCDC_LPCR_TFT (0x80000000) |
| 1414 | #define LCDC_LPCR_MODE_MONOCHROME (0x00000000) |
| 1415 | #define LCDC_LPCR_MODE_CSTN (0x40000000) |
| 1416 | #define LCDC_LPCR_MODE_TFT (0xC0000000) |
| 1417 | #define LCDC_LPCR_PBSIZ_1 (0x00000000) |
| 1418 | #define LCDC_LPCR_PBSIZ_2 (0x10000000) |
| 1419 | #define LCDC_LPCR_PBSIZ_4 (0x20000000) |
| 1420 | #define LCDC_LPCR_PBSIZ_8 (0x30000000) |
| 1421 | #define LCDC_LPCR_BPIX_1bpp (0x00000000) |
| 1422 | #define LCDC_LPCR_BPIX_2bpp (0x02000000) |
| 1423 | #define LCDC_LPCR_BPIX_4bpp (0x04000000) |
| 1424 | #define LCDC_LPCR_BPIX_8bpp (0x06000000) |
| 1425 | #define LCDC_LPCR_BPIX_12bpp (0x08000000) |
| 1426 | #define LCDC_LPCR_BPIX_16bpp (0x0A000000) |
| 1427 | #define LCDC_LPCR_BPIX_18bpp (0x0C000000) |
| 1428 | |
| 1429 | #define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) |
| 1430 | |
| 1431 | /* Bit definitions and macros for LCDC_LHCR */ |
| 1432 | #define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) |
| 1433 | #define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) |
| 1434 | #define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) |
| 1435 | |
| 1436 | /* Bit definitions and macros for LCDC_LVCR */ |
| 1437 | #define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) |
| 1438 | #define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) |
| 1439 | #define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) |
| 1440 | |
| 1441 | /* Bit definitions and macros for LCDC_LPOR */ |
| 1442 | #define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) |
| 1443 | |
| 1444 | /* Bit definitions and macros for LCDC_LPCCR */ |
| 1445 | #define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) |
| 1446 | #define LCDC_LPCCR_CC_EN (0x00000100) |
| 1447 | #define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) |
| 1448 | #define LCDC_LPCCR_LDMSK (0x00008000) |
| 1449 | #define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) |
| 1450 | #define LCDC_LPCCR_SCR_LINEPULSE (0x00000000) |
| 1451 | #define LCDC_LPCCR_SCR_PIXELCLK (0x00002000) |
| 1452 | #define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) |
| 1453 | |
| 1454 | /* Bit definitions and macros for LCDC_LDCR */ |
| 1455 | #define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) |
| 1456 | #define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) |
| 1457 | #define LCDC_LDCR_BURST (0x80000000) |
| 1458 | |
| 1459 | /* Bit definitions and macros for LCDC_LRMCR */ |
| 1460 | #define LCDC_LRMCR_SEL_REF (0x00000001) |
| 1461 | |
| 1462 | /* Bit definitions and macros for LCDC_LICR */ |
| 1463 | #define LCDC_LICR_INTCON (0x00000001) |
| 1464 | #define LCDC_LICR_INTSYN (0x00000004) |
| 1465 | #define LCDC_LICR_GW_INT_CON (0x00000010) |
| 1466 | |
| 1467 | /* Bit definitions and macros for LCDC_LIER */ |
| 1468 | #define LCDC_LIER_BOF_EN (0x00000001) |
| 1469 | #define LCDC_LIER_EOF_EN (0x00000002) |
| 1470 | #define LCDC_LIER_ERR_RES_EN (0x00000004) |
| 1471 | #define LCDC_LIER_UDR_ERR_EN (0x00000008) |
| 1472 | #define LCDC_LIER_GW_BOF_EN (0x00000010) |
| 1473 | #define LCDC_LIER_GW_EOF_EN (0x00000020) |
| 1474 | #define LCDC_LIER_GW_ERR_RES_EN (0x00000040) |
| 1475 | #define LCDC_LIER_GW_UDR_ERR_EN (0x00000080) |
| 1476 | |
| 1477 | /* Bit definitions and macros for LCDC_LISR */ |
| 1478 | #define LCDC_LISR_BOF (0x00000001) |
| 1479 | #define LCDC_LISR_EOF (0x00000002) |
| 1480 | #define LCDC_LISR_ERR_RES (0x00000004) |
| 1481 | #define LCDC_LISR_UDR_ERR (0x00000008) |
| 1482 | #define LCDC_LISR_GW_BOF (0x00000010) |
| 1483 | #define LCDC_LISR_GW_EOF (0x00000020) |
| 1484 | #define LCDC_LISR_GW_ERR_RES (0x00000040) |
| 1485 | #define LCDC_LISR_GW_UDR_ERR (0x00000080) |
| 1486 | |
| 1487 | /* Bit definitions and macros for LCDC_LGWSAR */ |
| 1488 | #define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) |
| 1489 | |
| 1490 | /* Bit definitions and macros for LCDC_LGWSR */ |
| 1491 | #define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) |
| 1492 | #define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) |
| 1493 | |
| 1494 | /* Bit definitions and macros for LCDC_LGWVPWR */ |
| 1495 | #define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) |
| 1496 | |
| 1497 | /* Bit definitions and macros for LCDC_LGWPOR */ |
| 1498 | #define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) |
| 1499 | |
| 1500 | /* Bit definitions and macros for LCDC_LGWPR */ |
| 1501 | #define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) |
| 1502 | #define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) |
| 1503 | |
| 1504 | /* Bit definitions and macros for LCDC_LGWCR */ |
| 1505 | #define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) |
| 1506 | #define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) |
| 1507 | #define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) |
| 1508 | #define LCDC_LGWCR_GW_RVS (0x00200000) |
| 1509 | #define LCDC_LGWCR_GWE (0x00400000) |
| 1510 | #define LCDC_LGWCR_GWCKE (0x00800000) |
| 1511 | #define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) |
| 1512 | |
| 1513 | /* Bit definitions and macros for LCDC_LGWDCR */ |
| 1514 | #define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) |
| 1515 | #define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) |
| 1516 | #define LCDC_LGWDCR_GWBT (0x80000000) |
| 1517 | |
| 1518 | /* Bit definitions and macros for LCDC_BPLUT_BASE */ |
| 1519 | #define LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) |
| 1520 | |
| 1521 | /* Bit definitions and macros for LCDC_GWLUT_BASE */ |
| 1522 | #define LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) |
| 1523 | |
| 1524 | /* not done yet */ |
| 1525 | /********************************************************************* |
| 1526 | * USB Controller (USB) |
| 1527 | *********************************************************************/ |
| 1528 | /* Bit definitions and macros for USB_HCSPARAMS */ |
| 1529 | #define USB_HCSPARAMS_N_PORTS(x) ((x)&0x0000000F) |
| 1530 | #define USB_HCSPARAMS_PPC (0x00000010) |
| 1531 | #define USB_HCSPARAMS_N_PCC(x) (((x)&0x0000000F)<<8) |
| 1532 | #define USB_HCSPARAMS_N_CC(x) (((x)&0x0000000F)<<12) |
| 1533 | #define USB_HCSPARAMS_PI (0x00010000) |
| 1534 | #define USB_HCSPARAMS_N_PTT(x) (((x)&0x0000000F)<<20) |
| 1535 | #define USB_HCSPARAMS_N_TT(x) (((x)&0x0000000F)<<24) |
| 1536 | |
| 1537 | /* Bit definitions and macros for USB_HCCPARAMS */ |
| 1538 | #define USB_HCCPARAMS_ADC (0x00000001) |
| 1539 | #define USB_HCCPARAMS_PFL (0x00000002) |
| 1540 | #define USB_HCCPARAMS_ASP (0x00000004) |
| 1541 | #define USB_HCCPARAMS_IST(x) (((x)&0x0000000F)<<4) |
| 1542 | #define USB_HCCPARAMS_EECP(x) (((x)&0x000000FF)<<8) |
| 1543 | |
| 1544 | /* Bit definitions and macros for USB_DCIVERSION */ |
| 1545 | #define USB_DCIVERSION_DCIVERSION(x) (((x)&0xFFFF)<<0) |
| 1546 | |
| 1547 | /* Bit definitions and macros for USB_DCCPARAMS */ |
| 1548 | #define USB_DCCPARAMS_DEN(x) (((x)&0x0000001F)<<0) |
| 1549 | #define USB_DCCPARAMS_DC (0x00000080) |
| 1550 | #define USB_DCCPARAMS_HC (0x00000100) |
| 1551 | |
| 1552 | /* Bit definitions and macros for USB_USBCMD */ |
| 1553 | #define USB_USBCMD_RS (0x00000001) |
| 1554 | #define USB_USBCMD_RST (0x00000002) |
| 1555 | #define USB_USBCMD_FS0 (0x00000004) |
| 1556 | #define USB_USBCMD_FS1 (0x00000008) |
| 1557 | #define USB_USBCMD_PSE (0x00000010) |
| 1558 | #define USB_USBCMD_ASE (0x00000020) |
| 1559 | #define USB_USBCMD_IAA (0x00000040) |
| 1560 | #define USB_USBCMD_LR (0x00000080) |
| 1561 | #define USB_USBCMD_ASP(x) (((x)&0x00000003)<<8) |
| 1562 | #define USB_USBCMD_ASPE (0x00000800) |
| 1563 | #define USB_USBCMD_SUTW (0x00002000) |
| 1564 | #define USB_USBCMD_ATDTW (0x00004000) |
| 1565 | #define USB_USBCMD_FS2 (0x00008000) |
| 1566 | #define USB_USBCMD_ITC(x) (((x)&0x000000FF)<<16) |
| 1567 | #define USB_USBCMD_ITC_IMM (0x00000000) |
| 1568 | #define USB_USBCMD_ITC_1 (0x00010000) |
| 1569 | #define USB_USBCMD_ITC_2 (0x00020000) |
| 1570 | #define USB_USBCMD_ITC_4 (0x00040000) |
| 1571 | #define USB_USBCMD_ITC_8 (0x00080000) |
| 1572 | #define USB_USBCMD_ITC_16 (0x00100000) |
| 1573 | #define USB_USBCMD_ITC_32 (0x00200000) |
| 1574 | #define USB_USBCMD_ITC_40 (0x00400000) |
| 1575 | #define USB_USBCMD_FS_1024 (0x00000000) |
| 1576 | #define USB_USBCMD_FS_512 (0x00000004) |
| 1577 | #define USB_USBCMD_FS_256 (0x00000008) |
| 1578 | #define USB_USBCMD_FS_128 (0x0000000C) |
| 1579 | #define USB_USBCMD_FS_64 (0x00008000) |
| 1580 | #define USB_USBCMD_FS_32 (0x00008004) |
| 1581 | #define USB_USBCMD_FS_16 (0x00008008) |
| 1582 | #define USB_USBCMD_FS_8 (0x0000800C) |
| 1583 | |
| 1584 | /* Bit definitions and macros for USB_USBSTS */ |
| 1585 | #define USB_USBSTS_UI (0x00000001) |
| 1586 | #define USB_USBSTS_UEI (0x00000002) |
| 1587 | #define USB_USBSTS_PCI (0x00000004) |
| 1588 | #define USB_USBSTS_FRI (0x00000008) |
| 1589 | #define USB_USBSTS_SEI (0x00000010) |
| 1590 | #define USB_USBSTS_AAI (0x00000020) |
| 1591 | #define USB_USBSTS_URI (0x00000040) |
| 1592 | #define USB_USBSTS_SRI (0x00000080) |
| 1593 | #define USB_USBSTS_SLI (0x00000100) |
| 1594 | #define USB_USBSTS_HCH (0x00001000) |
| 1595 | #define USB_USBSTS_RCL (0x00002000) |
| 1596 | #define USB_USBSTS_PS (0x00004000) |
| 1597 | #define USB_USBSTS_AS (0x00008000) |
| 1598 | |
| 1599 | /* Bit definitions and macros for USB_USBINTR */ |
| 1600 | #define USB_USBINTR_UE (0x00000001) |
| 1601 | #define USB_USBINTR_UEE (0x00000002) |
| 1602 | #define USB_USBINTR_PCE (0x00000004) |
| 1603 | #define USB_USBINTR_FRE (0x00000008) |
| 1604 | #define USB_USBINTR_SEE (0x00000010) |
| 1605 | #define USB_USBINTR_AAE (0x00000020) |
| 1606 | #define USB_USBINTR_URE (0x00000040) |
| 1607 | #define USB_USBINTR_SRE (0x00000080) |
| 1608 | #define USB_USBINTR_SLE (0x00000100) |
| 1609 | |
| 1610 | /* Bit definitions and macros for USB_FRINDEX */ |
| 1611 | #define USB_FRINDEX_FRINDEX(x) (((x)&0x00003FFF)<<0) |
| 1612 | |
| 1613 | /* Bit definitions and macros for USB_PERIODICLISTBASE */ |
| 1614 | #define USB_PERIODICLISTBASE_PERBASE(x) (((x)&0x000FFFFF)<<12) |
| 1615 | |
| 1616 | /* Bit definitions and macros for USB_DEVICEADDR */ |
| 1617 | #define USB_DEVICEADDR_USBADR(x) (((x)&0x0000007F)<<25) |
| 1618 | |
| 1619 | /* Bit definitions and macros for USB_ASYNCLISTADDR */ |
| 1620 | #define USB_ASYNCLISTADDR_ASYBASE(x) (((x)&0x07FFFFFF)<<5) |
| 1621 | |
| 1622 | /* Bit definitions and macros for USB_EPLISTADDR */ |
| 1623 | #define USB_EPLISTADDR_EPBASE(x) (((x)&0x001FFFFF)<<11) |
| 1624 | |
| 1625 | /* Bit definitions and macros for USB_ASNCTTSTS */ |
| 1626 | #define USB_ASNCTTSTS_TTAS (0x00000001) |
| 1627 | #define USB_ASNCTTSTS_TTAC (0x00000002) |
| 1628 | |
| 1629 | /* Bit definitions and macros for USB_BURSTSIZE */ |
| 1630 | #define USB_BURSTSIZE_RXPBURST(x) (((x)&0x000000FF)<<0) |
| 1631 | #define USB_BURSTSIZE_TXPBURST(x) (((x)&0x000000FF)<<8) |
| 1632 | |
| 1633 | /* Bit definitions and macros for USB_TXFILLTUNING */ |
| 1634 | #define USB_TXFILLTUNING_TXSCHOH(x) (((x)&0x000000FF)<<0) |
| 1635 | #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((x)&0x0000001F)<<8) |
| 1636 | #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((x)&0x0000003F)<<16) |
| 1637 | |
| 1638 | /* Bit definitions and macros for USB_TXTTFILLTUNING */ |
| 1639 | #define USB_TXTTFILLTUNING_TXTTSCHOH(x) (((x)&0x0000001F)<<0) |
| 1640 | #define USB_TXTTFILLTUNING_TXTTSCHHEALTH(x) (((x)&0x0000001F)<<8) |
| 1641 | |
| 1642 | /* Bit definitions and macros for USB_ULPI_VIEWPORT */ |
| 1643 | #define USB_ULPI_VIEWPORT_ULPI_DATWR(x) (((x)&0x000000FF)<<0) |
| 1644 | #define USB_ULPI_VIEWPORT_ULPI_DATRD(x) (((x)&0x000000FF)<<8) |
| 1645 | #define USB_ULPI_VIEWPORT_ULPI_ADDR(x) (((x)&0x000000FF)<<16) |
| 1646 | #define USB_ULPI_VIEWPORT_ULPI_PORT(x) (((x)&0x00000007)<<24) |
| 1647 | #define USB_ULPI_VIEWPORT_ULPI_SS (0x08000000) |
| 1648 | #define USB_ULPI_VIEWPORT_ULPI_RW (0x20000000) |
| 1649 | #define USB_ULPI_VIEWPORT_ULPI_RUN (0x40000000) |
| 1650 | #define USB_ULPI_VIEWPORT_ULPI_WU (0x80000000) |
| 1651 | |
| 1652 | /* Bit definitions and macros for USB_CONFIGFLAG */ |
| 1653 | #define USB_CONFIGFLAG_CONFIGFLAG(x) (((x)&0xFFFFFFFF)<<0) |
| 1654 | |
| 1655 | /* Bit definitions and macros for USB_PORTSC */ |
| 1656 | #define USB_PORTSC_CCS (0x00000001) |
| 1657 | #define USB_PORTSC_CSC (0x00000002) |
| 1658 | #define USB_PORTSC_PE (0x00000004) |
| 1659 | #define USB_PORTSC_PEC (0x00000008) |
| 1660 | #define USB_PORTSC_OCA (0x00000010) |
| 1661 | #define USB_PORTSC_OCC (0x00000020) |
| 1662 | #define USB_PORTSC_FPR (0x00000040) |
| 1663 | #define USB_PORTSC_SUSP (0x00000080) |
| 1664 | #define USB_PORTSC_PR (0x00000100) |
| 1665 | #define USB_PORTSC_LS(x) (((x)&0x00000003)<<10) |
| 1666 | #define USB_PORTSC_PP (0x00001000) |
| 1667 | #define USB_PORTSC_PO (0x00002000) |
| 1668 | #define USB_PORTSC_PIC(x) (((x)&0x00000003)<<14) |
| 1669 | #define USB_PORTSC_PTC(x) (((x)&0x0000000F)<<16) |
| 1670 | #define USB_PORTSC_WLCN (0x00100000) |
| 1671 | #define USB_PORTSC_WKDS (0x00200000) |
| 1672 | #define USB_PORTSC_WKOC (0x00400000) |
| 1673 | #define USB_PORTSC_PHCD (0x00800000) |
| 1674 | #define USB_PORTSC_PFSC (0x01000000) |
| 1675 | #define USB_PORTSC_PSPD(x) (((x)&0x00000003)<<26) |
| 1676 | #define USB_PORTSC_PTS(x) (((x)&0x00000003)<<30) |
| 1677 | #define USB_PORTSC_PTS_ULPI (0x80000000) |
| 1678 | #define USB_PORTSC_PTS_FS_LS (0xC0000000) |
| 1679 | #define USB_PORTSC_PSPD_FULL (0x00000000) |
| 1680 | #define USB_PORTSC_PSPD_LOW (0x04000000) |
| 1681 | #define USB_PORTSC_PSPD_HIGH (0x08000000) |
| 1682 | #define USB_PORTSC_PTC_DISBALE (0x00000000) |
| 1683 | #define USB_PORTSC_PTC_JSTATE (0x00010000) |
| 1684 | #define USB_PORTSC_PTC_KSTATE (0x00020000) |
| 1685 | #define USB_PORTSC_PTC_SEQ_NAK (0x00030000) |
| 1686 | #define USB_PORTSC_PTC_PACKET (0x00040000) |
| 1687 | #define USB_PORTSC_PTC_FORCE_ENABLE (0x00050000) |
| 1688 | #define USB_PORTSC_PIC_OFF (0x00000000) |
| 1689 | #define USB_PORTSC_PIC_AMBER (0x00004000) |
| 1690 | #define USB_PORTSC_PIC_GREEN (0x00008000) |
| 1691 | #define USB_PORTSC_LS_SE0 (0x00000000) |
| 1692 | #define USB_PORTSC_LS_JSTATE (0x00000400) |
| 1693 | #define USB_PORTSC_LS_KSTATE (0x00000800) |
| 1694 | |
| 1695 | /* Bit definitions and macros for USB_OTGSC */ |
| 1696 | #define USB_OTGSC_VD (0x00000001) |
| 1697 | #define USB_OTGSC_VC (0x00000002) |
| 1698 | #define USB_OTGSC_OT (0x00000008) |
| 1699 | #define USB_OTGSC_DP (0x00000010) |
| 1700 | #define USB_OTGSC_ID (0x00000100) |
| 1701 | #define USB_OTGSC_AVV (0x00000200) |
| 1702 | #define USB_OTGSC_ASV (0x00000400) |
| 1703 | #define USB_OTGSC_BSV (0x00000800) |
| 1704 | #define USB_OTGSC_BSE (0x00001000) |
| 1705 | #define USB_OTGSC_1MST (0x00002000) |
| 1706 | #define USB_OTGSC_DPS (0x00004000) |
| 1707 | #define USB_OTGSC_IDIS (0x00010000) |
| 1708 | #define USB_OTGSC_AVVIS (0x00020000) |
| 1709 | #define USB_OTGSC_ASVIS (0x00040000) |
| 1710 | #define USB_OTGSC_BSVIS (0x00080000) |
| 1711 | #define USB_OTGSC_BSEIS (0x00100000) |
| 1712 | #define USB_OTGSC_1MSS (0x00200000) |
| 1713 | #define USB_OTGSC_DPIS (0x00400000) |
| 1714 | #define USB_OTGSC_IDIE (0x01000000) |
| 1715 | #define USB_OTGSC_AVVIE (0x02000000) |
| 1716 | #define USB_OTGSC_ASVIE (0x04000000) |
| 1717 | #define USB_OTGSC_BSVIE (0x08000000) |
| 1718 | #define USB_OTGSC_BSEIE (0x10000000) |
| 1719 | #define USB_OTGSC_1MSE (0x20000000) |
| 1720 | #define USB_OTGSC_DPIE (0x40000000) |
| 1721 | #define USB_OTGSC_CLEAR (0x007F0000) |
| 1722 | #define USB_OTGSC_ENABLE_ALL (0x7F000000) |
| 1723 | |
| 1724 | /* Bit definitions and macros for USB_USBMODE */ |
| 1725 | #define USB_USBMODE_CM(x) (((x)&0x00000003)<<0) |
| 1726 | #define USB_USBMODE_SLOM (0x00000008) |
| 1727 | #define USB_USBMODE_SDIS (0x00000010) |
| 1728 | #define USB_USBMODE_CM_IDLE (0x00000000) |
| 1729 | #define USB_USBMODE_CM_DEVICE (0x00000002) |
| 1730 | #define USB_USBMODE_CM_HOST (0x00000003) |
| 1731 | #define USB_USBMODE_ES (0x00000004) |
| 1732 | |
| 1733 | /* Bit definitions and macros for USB_EPSETUPSR */ |
| 1734 | #define USB_EPSETUPSR_EPSETUPSTAT(x) (((x)&0x0000003F)<<0) |
| 1735 | |
| 1736 | /* Bit definitions and macros for USB_EPPRIME */ |
| 1737 | #define USB_EPPRIME_PERB(x) (((x)&0x0000003F)<<0) |
| 1738 | #define USB_EPPRIME_PETB(x) (((x)&0x0000003F)<<16) |
| 1739 | #define USB_EPPRIME_PETB0 (0x00010000) |
| 1740 | #define USB_EPPRIME_PETB1 (0x00020000) |
| 1741 | #define USB_EPPRIME_PETB2 (0x00040000) |
| 1742 | #define USB_EPPRIME_PETB3 (0x00080000) |
| 1743 | #define USB_EPPRIME_PETB4 (0x00100000) |
| 1744 | #define USB_EPPRIME_PETB5 (0x00200000) |
| 1745 | #define USB_EPPRIME_PERB0 (0x00000001) |
| 1746 | #define USB_EPPRIME_PERB1 (0x00000002) |
| 1747 | #define USB_EPPRIME_PERB2 (0x00000004) |
| 1748 | #define USB_EPPRIME_PERB3 (0x00000008) |
| 1749 | #define USB_EPPRIME_PERB4 (0x00000010) |
| 1750 | #define USB_EPPRIME_PERB5 (0x00000020) |
| 1751 | |
| 1752 | /* Bit definitions and macros for USB_EPFLUSH */ |
| 1753 | #define USB_EPFLUSH_FERB(x) (((x)&0x0000003F)<<0) |
| 1754 | #define USB_EPFLUSH_FETB(x) (((x)&0x0000003F)<<16) |
| 1755 | #define USB_EPFLUSH_FETB0 (0x00010000) |
| 1756 | #define USB_EPFLUSH_FETB1 (0x00020000) |
| 1757 | #define USB_EPFLUSH_FETB2 (0x00040000) |
| 1758 | #define USB_EPFLUSH_FETB3 (0x00080000) |
| 1759 | #define USB_EPFLUSH_FETB4 (0x00100000) |
| 1760 | #define USB_EPFLUSH_FETB5 (0x00200000) |
| 1761 | #define USB_EPFLUSH_FERB0 (0x00000001) |
| 1762 | #define USB_EPFLUSH_FERB1 (0x00000002) |
| 1763 | #define USB_EPFLUSH_FERB2 (0x00000004) |
| 1764 | #define USB_EPFLUSH_FERB3 (0x00000008) |
| 1765 | #define USB_EPFLUSH_FERB4 (0x00000010) |
| 1766 | #define USB_EPFLUSH_FERB5 (0x00000020) |
| 1767 | |
| 1768 | /* Bit definitions and macros for USB_EPSR */ |
| 1769 | #define USB_EPSR_ERBR(x) (((x)&0x0000003F)<<0) |
| 1770 | #define USB_EPSR_ETBR(x) (((x)&0x0000003F)<<16) |
| 1771 | #define USB_EPSR_ETBR0 (0x00010000) |
| 1772 | #define USB_EPSR_ETBR1 (0x00020000) |
| 1773 | #define USB_EPSR_ETBR2 (0x00040000) |
| 1774 | #define USB_EPSR_ETBR3 (0x00080000) |
| 1775 | #define USB_EPSR_ETBR4 (0x00100000) |
| 1776 | #define USB_EPSR_ETBR5 (0x00200000) |
| 1777 | #define USB_EPSR_ERBR0 (0x00000001) |
| 1778 | #define USB_EPSR_ERBR1 (0x00000002) |
| 1779 | #define USB_EPSR_ERBR2 (0x00000004) |
| 1780 | #define USB_EPSR_ERBR3 (0x00000008) |
| 1781 | #define USB_EPSR_ERBR4 (0x00000010) |
| 1782 | #define USB_EPSR_ERBR5 (0x00000020) |
| 1783 | |
| 1784 | /* Bit definitions and macros for USB_EPCOMPLETE */ |
| 1785 | #define USB_EPCOMPLETE_ERCE(x) (((x)&0x0000003F)<<0) |
| 1786 | #define USB_EPCOMPLETE_ETCE(x) (((x)&0x0000003F)<<16) |
| 1787 | #define USB_EPCOMPLETE_ETCE0 (0x00010000) |
| 1788 | #define USB_EPCOMPLETE_ETCE1 (0x00020000) |
| 1789 | #define USB_EPCOMPLETE_ETCE2 (0x00040000) |
| 1790 | #define USB_EPCOMPLETE_ETCE3 (0x00080000) |
| 1791 | #define USB_EPCOMPLETE_ETCE4 (0x00100000) |
| 1792 | #define USB_EPCOMPLETE_ETCE5 (0x00200000) |
| 1793 | #define USB_EPCOMPLETE_ERCE0 (0x00000001) |
| 1794 | #define USB_EPCOMPLETE_ERCE1 (0x00000002) |
| 1795 | #define USB_EPCOMPLETE_ERCE2 (0x00000004) |
| 1796 | #define USB_EPCOMPLETE_ERCE3 (0x00000008) |
| 1797 | #define USB_EPCOMPLETE_ERCE4 (0x00000010) |
| 1798 | #define USB_EPCOMPLETE_ERCE5 (0x00000020) |
| 1799 | |
| 1800 | /* Bit definitions and macros for USB_EPCR0 */ |
| 1801 | #define USB_EPCR0_RXS (0x00000001) |
| 1802 | #define USB_EPCR0_RXT(x) (((x)&0x00000003)<<2) |
| 1803 | #define USB_EPCR0_RXE (0x00000080) |
| 1804 | #define USB_EPCR0_TXS (0x00010000) |
| 1805 | #define USB_EPCR0_TXT(x) (((x)&0x00000003)<<18) |
| 1806 | #define USB_EPCR0_TXE (0x00800000) |
| 1807 | |
| 1808 | /* Bit definitions and macros for USB_EPCR */ |
| 1809 | #define USB_EPCR_RXS (0x00000001) |
| 1810 | #define USB_EPCR_RXD (0x00000002) |
| 1811 | #define USB_EPCR_RXT(x) (((x)&0x00000003)<<2) |
| 1812 | #define USB_EPCR_RXI (0x00000020) |
| 1813 | #define USB_EPCR_RXR (0x00000040) |
| 1814 | #define USB_EPCR_RXE (0x00000080) |
| 1815 | #define USB_EPCR_TXS (0x00010000) |
| 1816 | #define USB_EPCR_TXD (0x00020000) |
| 1817 | #define USB_EPCR_TXT(x) (((x)&0x00000003)<<18) |
| 1818 | #define USB_EPCR_TXI (0x00200000) |
| 1819 | #define USB_EPCR_TXR (0x00400000) |
| 1820 | #define USB_EPCR_TXE (0x00800000) |
| 1821 | #define USB_EPCR_TXT_CONTROL (0x00000000) |
| 1822 | #define USB_EPCR_TXT_ISO (0x00040000) |
| 1823 | #define USB_EPCR_TXT_BULK (0x00080000) |
| 1824 | #define USB_EPCR_TXT_INT (0x000C0000) |
| 1825 | #define USB_EPCR_RXT_CONTROL (0x00000000) |
| 1826 | #define USB_EPCR_RXT_ISO (0x00000004) |
| 1827 | #define USB_EPCR_RXT_BULK (0x00000008) |
| 1828 | #define USB_EPCR_RXT_INT (0x0000000C) |
| 1829 | |
| 1830 | /********************************************************************* |
| 1831 | * SDRAM Controller (SDRAMC) |
| 1832 | *********************************************************************/ |
| 1833 | /* Bit definitions and macros for SDRAMC_SDMR */ |
| 1834 | #define SDRAMC_SDMR_BNKAD_LEMR (0x40000000) |
| 1835 | #define SDRAMC_SDMR_BNKAD_LMR (0x00000000) |
| 1836 | #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) |
| 1837 | #define SDRAMC_SDMR_CMD (0x00010000) |
| 1838 | |
| 1839 | /* Bit definitions and macros for SDRAMC_SDCR */ |
| 1840 | #define SDRAMC_SDCR_MODE_EN (0x80000000) |
| 1841 | #define SDRAMC_SDCR_CKE (0x40000000) |
| 1842 | #define SDRAMC_SDCR_DDR (0x20000000) |
| 1843 | #define SDRAMC_SDCR_REF (0x10000000) |
| 1844 | #define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) |
| 1845 | #define SDRAMC_SDCR_OE_RULE (0x00400000) |
| 1846 | #define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) |
| 1847 | #define SDRAMC_SDCR_PS_32 (0x00000000) |
| 1848 | #define SDRAMC_SDCR_PS_16 (0x00002000) |
| 1849 | #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) |
| 1850 | #define SDRAMC_SDCR_IREF (0x00000004) |
| 1851 | #define SDRAMC_SDCR_IPALL (0x00000002) |
| 1852 | |
| 1853 | /* Bit definitions and macros for SDRAMC_SDCFG1 */ |
| 1854 | #define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) |
| 1855 | #define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) |
| 1856 | #define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) |
| 1857 | #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) |
| 1858 | #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) |
| 1859 | #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) |
| 1860 | #define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) |
| 1861 | |
| 1862 | /* Bit definitions and macros for SDRAMC_SDCFG2 */ |
| 1863 | #define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) |
| 1864 | #define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) |
| 1865 | #define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) |
| 1866 | #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) |
| 1867 | |
| 1868 | /* Bit definitions and macros for SDRAMC_SDDS */ |
| 1869 | #define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) |
| 1870 | #define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) |
| 1871 | #define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) |
| 1872 | #define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) |
| 1873 | #define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003) |
| 1874 | |
| 1875 | /* Bit definitions and macros for SDRAMC_SDCS */ |
| 1876 | #define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) |
| 1877 | #define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F) |
| 1878 | #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) |
| 1879 | #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) |
| 1880 | #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) |
| 1881 | #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) |
| 1882 | #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) |
| 1883 | #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) |
| 1884 | #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) |
| 1885 | #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) |
| 1886 | #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) |
| 1887 | #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) |
| 1888 | #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) |
| 1889 | #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) |
| 1890 | #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) |
| 1891 | #define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) |
| 1892 | |
| 1893 | /********************************************************************* |
| 1894 | * Synchronous Serial Interface (SSI) |
| 1895 | *********************************************************************/ |
| 1896 | /* Bit definitions and macros for SSI_CR */ |
| 1897 | #define SSI_CR_CIS (0x00000200) |
| 1898 | #define SSI_CR_TCH (0x00000100) |
| 1899 | #define SSI_CR_MCE (0x00000080) |
| 1900 | #define SSI_CR_I2S_SLAVE (0x00000040) |
| 1901 | #define SSI_CR_I2S_MASTER (0x00000020) |
| 1902 | #define SSI_CR_I2S_NORMAL (0x00000000) |
| 1903 | #define SSI_CR_SYN (0x00000010) |
| 1904 | #define SSI_CR_NET (0x00000008) |
| 1905 | #define SSI_CR_RE (0x00000004) |
| 1906 | #define SSI_CR_TE (0x00000002) |
| 1907 | #define SSI_CR_SSI_EN (0x00000001) |
| 1908 | |
| 1909 | /* Bit definitions and macros for SSI_ISR */ |
| 1910 | #define SSI_ISR_CMDAU (0x00040000) |
| 1911 | #define SSI_ISR_CMDDU (0x00020000) |
| 1912 | #define SSI_ISR_RXT (0x00010000) |
| 1913 | #define SSI_ISR_RDR1 (0x00008000) |
| 1914 | #define SSI_ISR_RDR0 (0x00004000) |
| 1915 | #define SSI_ISR_TDE1 (0x00002000) |
| 1916 | #define SSI_ISR_TDE0 (0x00001000) |
| 1917 | #define SSI_ISR_ROE1 (0x00000800) |
| 1918 | #define SSI_ISR_ROE0 (0x00000400) |
| 1919 | #define SSI_ISR_TUE1 (0x00000200) |
| 1920 | #define SSI_ISR_TUE0 (0x00000100) |
| 1921 | #define SSI_ISR_TFS (0x00000080) |
| 1922 | #define SSI_ISR_RFS (0x00000040) |
| 1923 | #define SSI_ISR_TLS (0x00000020) |
| 1924 | #define SSI_ISR_RLS (0x00000010) |
| 1925 | #define SSI_ISR_RFF1 (0x00000008) |
| 1926 | #define SSI_ISR_RFF0 (0x00000004) |
| 1927 | #define SSI_ISR_TFE1 (0x00000002) |
| 1928 | #define SSI_ISR_TFE0 (0x00000001) |
| 1929 | |
| 1930 | /* Bit definitions and macros for SSI_IER */ |
| 1931 | #define SSI_IER_RDMAE (0x00400000) |
| 1932 | #define SSI_IER_RIE (0x00200000) |
| 1933 | #define SSI_IER_TDMAE (0x00100000) |
| 1934 | #define SSI_IER_TIE (0x00080000) |
| 1935 | #define SSI_IER_CMDAU (0x00040000) |
| 1936 | #define SSI_IER_CMDU (0x00020000) |
| 1937 | #define SSI_IER_RXT (0x00010000) |
| 1938 | #define SSI_IER_RDR1 (0x00008000) |
| 1939 | #define SSI_IER_RDR0 (0x00004000) |
| 1940 | #define SSI_IER_TDE1 (0x00002000) |
| 1941 | #define SSI_IER_TDE0 (0x00001000) |
| 1942 | #define SSI_IER_ROE1 (0x00000800) |
| 1943 | #define SSI_IER_ROE0 (0x00000400) |
| 1944 | #define SSI_IER_TUE1 (0x00000200) |
| 1945 | #define SSI_IER_TUE0 (0x00000100) |
| 1946 | #define SSI_IER_TFS (0x00000080) |
| 1947 | #define SSI_IER_RFS (0x00000040) |
| 1948 | #define SSI_IER_TLS (0x00000020) |
| 1949 | #define SSI_IER_RLS (0x00000010) |
| 1950 | #define SSI_IER_RFF1 (0x00000008) |
| 1951 | #define SSI_IER_RFF0 (0x00000004) |
| 1952 | #define SSI_IER_TFE1 (0x00000002) |
| 1953 | #define SSI_IER_TFE0 (0x00000001) |
| 1954 | |
| 1955 | /* Bit definitions and macros for SSI_TCR */ |
| 1956 | #define SSI_TCR_TXBIT0 (0x00000200) |
| 1957 | #define SSI_TCR_TFEN1 (0x00000100) |
| 1958 | #define SSI_TCR_TFEN0 (0x00000080) |
| 1959 | #define SSI_TCR_TFDIR (0x00000040) |
| 1960 | #define SSI_TCR_TXDIR (0x00000020) |
| 1961 | #define SSI_TCR_TSHFD (0x00000010) |
| 1962 | #define SSI_TCR_TSCKP (0x00000008) |
| 1963 | #define SSI_TCR_TFSI (0x00000004) |
| 1964 | #define SSI_TCR_TFSL (0x00000002) |
| 1965 | #define SSI_TCR_TEFS (0x00000001) |
| 1966 | |
| 1967 | /* Bit definitions and macros for SSI_RCR */ |
| 1968 | #define SSI_RCR_RXEXT (0x00000400) |
| 1969 | #define SSI_RCR_RXBIT0 (0x00000200) |
| 1970 | #define SSI_RCR_RFEN1 (0x00000100) |
| 1971 | #define SSI_RCR_RFEN0 (0x00000080) |
| 1972 | #define SSI_RCR_RSHFD (0x00000010) |
| 1973 | #define SSI_RCR_RSCKP (0x00000008) |
| 1974 | #define SSI_RCR_RFSI (0x00000004) |
| 1975 | #define SSI_RCR_RFSL (0x00000002) |
| 1976 | #define SSI_RCR_REFS (0x00000001) |
| 1977 | |
| 1978 | /* Bit definitions and macros for SSI_CCR */ |
| 1979 | #define SSI_CCR_DIV2 (0x00040000) |
| 1980 | #define SSI_CCR_PSR (0x00020000) |
| 1981 | #define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) |
| 1982 | #define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) |
| 1983 | #define SSI_CCR_PM(x) ((x)&0x000000FF) |
| 1984 | |
| 1985 | /* Bit definitions and macros for SSI_FCSR */ |
| 1986 | #define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) |
| 1987 | #define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) |
| 1988 | #define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) |
| 1989 | #define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) |
| 1990 | #define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) |
| 1991 | #define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) |
| 1992 | #define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) |
| 1993 | #define SSI_FCSR_TFWM0(x) ((x)&0x0000000F) |
| 1994 | |
| 1995 | /* Bit definitions and macros for SSI_ACR */ |
| 1996 | #define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) |
| 1997 | #define SSI_ACR_WR (0x00000010) |
| 1998 | #define SSI_ACR_RD (0x00000008) |
| 1999 | #define SSI_ACR_TIF (0x00000004) |
| 2000 | #define SSI_ACR_FV (0x00000002) |
| 2001 | #define SSI_ACR_AC97EN (0x00000001) |
| 2002 | |
| 2003 | /* Bit definitions and macros for SSI_ACADD */ |
| 2004 | #define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF) |
| 2005 | |
| 2006 | /* Bit definitions and macros for SSI_ACDAT */ |
| 2007 | #define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF) |
| 2008 | |
| 2009 | /* Bit definitions and macros for SSI_ATAG */ |
| 2010 | #define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF) |
| 2011 | |
| 2012 | /********************************************************************* |
| 2013 | * Phase Locked Loop (PLL) |
| 2014 | *********************************************************************/ |
| 2015 | /* Bit definitions and macros for PLL_PODR */ |
| 2016 | #define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) |
| 2017 | #define PLL_PODR_BUSDIV(x) ((x)&0x0F) |
| 2018 | |
| 2019 | /* Bit definitions and macros for PLL_PLLCR */ |
| 2020 | #define PLL_PLLCR_DITHEN (0x80) |
| 2021 | #define PLL_PLLCR_DITHDEV(x) ((x)&0x07) |
| 2022 | |
| 2023 | #endif /* mcf5329_h */ |