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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Patrick Bruennba81b042016-11-04 11:57:02 +01002/*
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 *
6 * Configuration settings for Beckhoff CX9020.
7 *
8 * Based on Freescale's Linux i.MX mx53loco.h file:
9 * Copyright (C) 2010-2011 Freescale Semiconductor.
Patrick Bruennba81b042016-11-04 11:57:02 +010010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#include <asm/arch/imx-regs.h>
16
17#define CONFIG_CMDLINE_TAG
18#define CONFIG_SETUP_MEMORY_TAGS
19#define CONFIG_INITRD_TAG
20
21#define CONFIG_SYS_FSL_CLK
22
23/* Size of malloc() pool */
24#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
25
Patrick Bruennba81b042016-11-04 11:57:02 +010026#define CONFIG_REVISION_TAG
27
28#define CONFIG_MXC_UART_BASE UART2_BASE
29
30#define CONFIG_FPGA_COUNT 1
31
32/* MMC Configs */
Patrick Bruennba81b042016-11-04 11:57:02 +010033#define CONFIG_SYS_FSL_ESDHC_ADDR 0
34#define CONFIG_SYS_FSL_ESDHC_NUM 2
35
Patrick Bruennba81b042016-11-04 11:57:02 +010036/* bootz: zImage/initrd.img support */
Patrick Bruennba81b042016-11-04 11:57:02 +010037
38/* Eth Configs */
Patrick Bruennba81b042016-11-04 11:57:02 +010039#define IMX_FEC_BASE FEC_BASE_ADDR
40#define CONFIG_ETHPRIME "FEC0"
41#define CONFIG_FEC_MXC_PHYADDR 0x1F
42
43/* USB Configs */
Patrick Bruennba81b042016-11-04 11:57:02 +010044#define CONFIG_USB_EHCI_MX5
Patrick Bruennba81b042016-11-04 11:57:02 +010045#define CONFIG_MXC_USB_PORT 1
46#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
47#define CONFIG_MXC_USB_FLAGS 0
48
49/* allow to overwrite serial and ethaddr */
50#define CONFIG_ENV_OVERWRITE
Patrick Bruennba81b042016-11-04 11:57:02 +010051
52/* Command definition */
Patrick Bruennba81b042016-11-04 11:57:02 +010053
54#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */
Patrick Bruennba81b042016-11-04 11:57:02 +010055
56#define CONFIG_EXTRA_ENV_SETTINGS \
Patrick Bruenn3876a352017-07-11 11:23:20 +020057 "fdt_addr_r=0x71ff0000\0" \
Patrick Bruenn2ef943e2017-07-11 11:23:21 +020058 "pxefile_addr_r=0x73000000\0" \
Patrick Bruenn3876a352017-07-11 11:23:20 +020059 "ramdisk_addr_r=0x72000000\0" \
Patrick Bruennba81b042016-11-04 11:57:02 +010060 "console=ttymxc1,115200\0" \
61 "uenv=/boot/uEnv.txt\0" \
62 "optargs=\0" \
63 "cmdline=\0" \
64 "mmcdev=0\0" \
65 "mmcpart=1\0" \
66 "mmcrootfstype=ext4 rootwait fixrtc\0" \
67 "mmcargs=setenv bootargs console=${console} " \
68 "${optargs} " \
69 "root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \
70 "rootfstype=${mmcrootfstype} " \
71 "${cmdline}\0" \
72 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
Patrick Bruenn2ef943e2017-07-11 11:23:21 +020073 "loadpxe=dhcp;setenv kernel_addr_r ${loadaddr};pxe get;pxe boot;\0" \
Patrick Bruenn3876a352017-07-11 11:23:20 +020074 "loadrd=load mmc ${bootpart} ${ramdisk_addr_r} ${bootdir}/${rdfile};" \
Patrick Bruennba81b042016-11-04 11:57:02 +010075 "setenv rdsize ${filesize}\0" \
76 "loadfdt=echo loading ${fdt_path} ...;" \
Patrick Bruenn3876a352017-07-11 11:23:20 +020077 "load mmc ${bootpart} ${fdt_addr_r} ${fdt_path}\0" \
Patrick Bruennba81b042016-11-04 11:57:02 +010078 "mmcboot=mmc dev ${mmcdev}; " \
79 "if mmc rescan; then " \
80 "echo SD/MMC found on device ${mmcdev};" \
81 "echo Checking for: ${uenv} ...;" \
82 "setenv bootpart ${mmcdev}:${mmcpart};" \
83 "if test -e mmc ${bootpart} ${uenv}; then " \
84 "load mmc ${bootpart} ${loadaddr} ${uenv};" \
85 "env import -t ${loadaddr} ${filesize};" \
86 "echo Loaded environment from ${uenv};" \
87 "if test -n ${dtb}; then " \
88 "setenv fdt_file ${dtb};" \
89 "echo Using: dtb=${fdt_file} ...;" \
90 "fi;" \
91 "echo Checking for uname_r in ${uenv}...;" \
92 "if test -n ${uname_r}; then " \
93 "echo Running uname_boot ...;" \
94 "run uname_boot;" \
95 "fi;" \
96 "fi;" \
97 "fi;\0" \
98 "uname_boot="\
99 "setenv bootdir /boot; " \
100 "setenv bootfile vmlinuz-${uname_r}; " \
101 "setenv ccatfile /boot/ccat.rbf; " \
102 "echo loading CCAT firmware from ${ccatfile}; " \
103 "load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \
104 "fpga load 0 ${loadaddr} ${filesize}; " \
105 "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
106 "echo loading ${bootdir}/${bootfile} ...; " \
107 "run loadimage;" \
108 "setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \
109 "if test -e mmc ${bootpart} ${fdt_path}; then " \
110 "run loadfdt;" \
111 "else " \
112 "echo; echo unable to find ${fdt_file} ...;" \
113 "echo booting legacy ...;"\
114 "run mmcargs;" \
115 "echo debug: [${bootargs}] ... ;" \
116 "echo debug: [bootz ${loadaddr}] ... ;" \
117 "bootz ${loadaddr}; " \
118 "fi;" \
119 "run mmcargs;" \
120 "echo debug: [${bootargs}] ... ;" \
Patrick Bruenn3876a352017-07-11 11:23:20 +0200121 "echo debug: [bootz ${loadaddr} - ${fdt_addr_r}];" \
122 "bootz ${loadaddr} - ${fdt_addr_r}; " \
Patrick Bruenn2ef943e2017-07-11 11:23:21 +0200123 "else " \
124 "echo loading from dhcp ...; " \
125 "run loadpxe; " \
Patrick Bruennba81b042016-11-04 11:57:02 +0100126 "fi;\0"
127
128#define CONFIG_BOOTCOMMAND \
129 "run mmcboot;"
130
131#define CONFIG_ARP_TIMEOUT 200UL
132
133/* Miscellaneous configurable options */
Patrick Bruennba81b042016-11-04 11:57:02 +0100134#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
135
Patrick Bruennba81b042016-11-04 11:57:02 +0100136#define CONFIG_SYS_MEMTEST_START 0x70000000
137#define CONFIG_SYS_MEMTEST_END 0x70010000
138
139#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
140
Patrick Bruennba81b042016-11-04 11:57:02 +0100141/* Physical Memory Map */
Patrick Bruennba81b042016-11-04 11:57:02 +0100142#define PHYS_SDRAM_1 CSD0_BASE_ADDR
143#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
144#define PHYS_SDRAM_2 CSD1_BASE_ADDR
145#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
146#define PHYS_SDRAM_SIZE (gd->ram_size)
147
148#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
149#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
150#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
151
152#define CONFIG_SYS_INIT_SP_OFFSET \
153 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154#define CONFIG_SYS_INIT_SP_ADDR \
155 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
156
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900157/* environment organization */
Patrick Bruennba81b042016-11-04 11:57:02 +0100158#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
159#define CONFIG_ENV_SIZE (8 * 1024)
Patrick Bruennba81b042016-11-04 11:57:02 +0100160#define CONFIG_SYS_MMC_ENV_DEV 0
161
162/* Framebuffer and LCD */
163#define CONFIG_PREBOOT
Patrick Bruennba81b042016-11-04 11:57:02 +0100164#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
165#define CONFIG_VIDEO_BMP_RLE8
166#define CONFIG_SPLASH_SCREEN
167#define CONFIG_BMP_16BPP
168#define CONFIG_VIDEO_LOGO
Patrick Bruennba81b042016-11-04 11:57:02 +0100169
170#endif /* __CONFIG_H */