York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/system.h> |
| 10 | #include <asm/armv8/mmu.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/arch-fsl-lsch3/immap_lsch3.h> |
Bhupesh Sharma | 25b8efe | 2015-03-19 09:20:43 -0700 | [diff] [blame] | 13 | #include <fsl_debug_server.h> |
J. German Rivera | 43e4ae3 | 2015-01-06 13:19:02 -0800 | [diff] [blame] | 14 | #include <fsl-mc/fsl_mc.h> |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 15 | #include "cpu.h" |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 16 | #include "mp.h" |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 17 | #include "speed.h" |
| 18 | |
| 19 | DECLARE_GLOBAL_DATA_PTR; |
| 20 | |
| 21 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 22 | /* |
| 23 | * To start MMU before DDR is available, we create MMU table in SRAM. |
| 24 | * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three |
| 25 | * levels of translation tables here to cover 40-bit address space. |
| 26 | * We use 4KB granule size, with 40 bits physical address, T0SZ=24 |
| 27 | * Level 0 IA[39], table address @0 |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 28 | * Level 1 IA[31:30], table address @0x1000, 0x2000 |
| 29 | * Level 2 IA[29:21], table address @0x3000, 0x4000 |
| 30 | * Address above 0x5000 is free for other purpose. |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 31 | */ |
| 32 | |
| 33 | #define SECTION_SHIFT_L0 39UL |
| 34 | #define SECTION_SHIFT_L1 30UL |
| 35 | #define SECTION_SHIFT_L2 21UL |
| 36 | #define BLOCK_SIZE_L0 0x8000000000UL |
| 37 | #define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) |
| 38 | #define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) |
| 39 | #define CONFIG_SYS_IFC_BASE 0x30000000 |
| 40 | #define CONFIG_SYS_IFC_SIZE 0x10000000 |
| 41 | #define CONFIG_SYS_IFC_BASE2 0x500000000 |
| 42 | #define CONFIG_SYS_IFC_SIZE2 0x100000000 |
| 43 | #define TCR_EL2_PS_40BIT (2 << 16) |
| 44 | #define LSCH3_VA_BITS (40) |
| 45 | #define LSCH3_TCR (TCR_TG0_4K | \ |
| 46 | TCR_EL2_PS_40BIT | \ |
| 47 | TCR_SHARED_NON | \ |
| 48 | TCR_ORGN_NC | \ |
| 49 | TCR_IRGN_NC | \ |
| 50 | TCR_T0SZ(LSCH3_VA_BITS)) |
| 51 | |
| 52 | /* |
| 53 | * Final MMU |
| 54 | * Let's start from the same layout as early MMU and modify as needed. |
| 55 | * IFC regions will be cache-inhibit. |
| 56 | */ |
| 57 | #define FINAL_QBMAN_CACHED_MEM 0x818000000UL |
| 58 | #define FINAL_QBMAN_CACHED_SIZE 0x4000000 |
| 59 | |
| 60 | |
| 61 | static inline void early_mmu_setup(void) |
| 62 | { |
| 63 | int el; |
| 64 | u64 i; |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 65 | u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1; |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 66 | u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; |
| 67 | u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); |
| 68 | u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 69 | u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); |
| 70 | u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 71 | |
| 72 | level0_table[0] = |
| 73 | (u64)level1_table_0 | PMD_TYPE_TABLE; |
| 74 | level0_table[1] = |
| 75 | (u64)level1_table_1 | PMD_TYPE_TABLE; |
| 76 | |
| 77 | /* |
| 78 | * set level 1 table 0 to cache_inhibit, covering 0 to 512GB |
| 79 | * set level 1 table 1 to cache enabled, covering 512GB to 1TB |
| 80 | * set level 2 table to cache-inhibit, covering 0 to 1GB |
| 81 | */ |
| 82 | section_l1t0 = 0; |
| 83 | section_l1t1 = BLOCK_SIZE_L0; |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 84 | section_l2t0 = 0; |
| 85 | section_l2t1 = CONFIG_SYS_FLASH_BASE; |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 86 | for (i = 0; i < 512; i++) { |
| 87 | set_pgtable_section(level1_table_0, i, section_l1t0, |
| 88 | MT_DEVICE_NGNRNE); |
| 89 | set_pgtable_section(level1_table_1, i, section_l1t1, |
| 90 | MT_NORMAL); |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 91 | set_pgtable_section(level2_table_0, i, section_l2t0, |
| 92 | MT_DEVICE_NGNRNE); |
| 93 | set_pgtable_section(level2_table_1, i, section_l2t1, |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 94 | MT_DEVICE_NGNRNE); |
| 95 | section_l1t0 += BLOCK_SIZE_L1; |
| 96 | section_l1t1 += BLOCK_SIZE_L1; |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 97 | section_l2t0 += BLOCK_SIZE_L2; |
| 98 | section_l2t1 += BLOCK_SIZE_L2; |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | level1_table_0[0] = |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 102 | (u64)level2_table_0 | PMD_TYPE_TABLE; |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 103 | level1_table_0[1] = |
| 104 | 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT | |
| 105 | PMD_ATTRINDX(MT_DEVICE_NGNRNE); |
| 106 | level1_table_0[2] = |
| 107 | 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | |
| 108 | PMD_ATTRINDX(MT_NORMAL); |
| 109 | level1_table_0[3] = |
| 110 | 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | |
| 111 | PMD_ATTRINDX(MT_NORMAL); |
| 112 | |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 113 | /* Rewerite table to enable cache for OCRAM */ |
| 114 | set_pgtable_section(level2_table_0, |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 115 | CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, |
| 116 | CONFIG_SYS_FSL_OCRAM_BASE, |
| 117 | MT_NORMAL); |
York Sun | 820a18f | 2015-03-20 19:28:11 -0700 | [diff] [blame] | 118 | |
| 119 | #if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY) |
| 120 | /* Rewrite table to enable cache for two entries (4MB) */ |
| 121 | section_l2t1 = CONFIG_SYS_IFC_BASE; |
| 122 | set_pgtable_section(level2_table_0, |
| 123 | section_l2t1 >> SECTION_SHIFT_L2, |
| 124 | section_l2t1, |
| 125 | MT_NORMAL); |
| 126 | section_l2t1 += BLOCK_SIZE_L2; |
| 127 | set_pgtable_section(level2_table_0, |
| 128 | section_l2t1 >> SECTION_SHIFT_L2, |
| 129 | section_l2t1, |
| 130 | MT_NORMAL); |
| 131 | #endif |
| 132 | |
| 133 | /* Create a mapping for 256MB IFC region to final flash location */ |
| 134 | level1_table_0[CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1] = |
| 135 | (u64)level2_table_1 | PMD_TYPE_TABLE; |
| 136 | section_l2t1 = CONFIG_SYS_IFC_BASE; |
| 137 | for (i = 0; i < 0x10000000 >> SECTION_SHIFT_L2; i++) { |
| 138 | set_pgtable_section(level2_table_1, i, |
| 139 | section_l2t1, MT_DEVICE_NGNRNE); |
| 140 | section_l2t1 += BLOCK_SIZE_L2; |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | el = current_el(); |
| 144 | set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES); |
| 145 | set_sctlr(get_sctlr() | CR_M); |
| 146 | } |
| 147 | |
| 148 | /* |
| 149 | * This final tale looks similar to early table, but different in detail. |
| 150 | * These tables are in regular memory. Cache on IFC is disabled. One sub table |
| 151 | * is added to enable cache for QBMan. |
| 152 | */ |
| 153 | static inline void final_mmu_setup(void) |
| 154 | { |
| 155 | int el; |
| 156 | u64 i, tbl_base, tbl_limit, section_base; |
| 157 | u64 section_l1t0, section_l1t1, section_l2; |
| 158 | u64 *level0_table = (u64 *)gd->arch.tlb_addr; |
| 159 | u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000); |
| 160 | u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000); |
| 161 | u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000); |
| 162 | u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000); |
| 163 | |
| 164 | |
| 165 | level0_table[0] = |
| 166 | (u64)level1_table_0 | PMD_TYPE_TABLE; |
| 167 | level0_table[1] = |
| 168 | (u64)level1_table_1 | PMD_TYPE_TABLE; |
| 169 | |
| 170 | /* |
| 171 | * set level 1 table 0 to cache_inhibit, covering 0 to 512GB |
| 172 | * set level 1 table 1 to cache enabled, covering 512GB to 1TB |
| 173 | * set level 2 table 0 to cache-inhibit, covering 0 to 1GB |
| 174 | */ |
| 175 | section_l1t0 = 0; |
York Sun | 2e3ad39 | 2015-01-06 13:11:22 -0800 | [diff] [blame] | 176 | section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE; |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 177 | section_l2 = 0; |
| 178 | for (i = 0; i < 512; i++) { |
| 179 | set_pgtable_section(level1_table_0, i, section_l1t0, |
| 180 | MT_DEVICE_NGNRNE); |
| 181 | set_pgtable_section(level1_table_1, i, section_l1t1, |
| 182 | MT_NORMAL); |
| 183 | set_pgtable_section(level2_table_0, i, section_l2, |
| 184 | MT_DEVICE_NGNRNE); |
| 185 | section_l1t0 += BLOCK_SIZE_L1; |
| 186 | section_l1t1 += BLOCK_SIZE_L1; |
| 187 | section_l2 += BLOCK_SIZE_L2; |
| 188 | } |
| 189 | |
| 190 | level1_table_0[0] = |
| 191 | (u64)level2_table_0 | PMD_TYPE_TABLE; |
| 192 | level1_table_0[2] = |
| 193 | 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | |
York Sun | 2e3ad39 | 2015-01-06 13:11:22 -0800 | [diff] [blame] | 194 | PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 195 | level1_table_0[3] = |
| 196 | 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | |
York Sun | 2e3ad39 | 2015-01-06 13:11:22 -0800 | [diff] [blame] | 197 | PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 198 | |
| 199 | /* Rewrite table to enable cache */ |
| 200 | set_pgtable_section(level2_table_0, |
| 201 | CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, |
| 202 | CONFIG_SYS_FSL_OCRAM_BASE, |
| 203 | MT_NORMAL); |
| 204 | |
| 205 | /* |
| 206 | * Fill in other part of tables if cache is needed |
| 207 | * If finer granularity than 1GB is needed, sub table |
| 208 | * should be created. |
| 209 | */ |
| 210 | section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1); |
| 211 | i = section_base >> SECTION_SHIFT_L1; |
| 212 | level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE; |
| 213 | section_l2 = section_base; |
| 214 | for (i = 0; i < 512; i++) { |
| 215 | set_pgtable_section(level2_table_1, i, section_l2, |
| 216 | MT_DEVICE_NGNRNE); |
| 217 | section_l2 += BLOCK_SIZE_L2; |
| 218 | } |
| 219 | tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); |
| 220 | tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) & |
| 221 | (BLOCK_SIZE_L1 - 1); |
| 222 | for (i = tbl_base >> SECTION_SHIFT_L2; |
| 223 | i < tbl_limit >> SECTION_SHIFT_L2; i++) { |
| 224 | section_l2 = section_base + (i << SECTION_SHIFT_L2); |
| 225 | set_pgtable_section(level2_table_1, i, |
| 226 | section_l2, MT_NORMAL); |
| 227 | } |
| 228 | |
| 229 | /* flush new MMU table */ |
| 230 | flush_dcache_range(gd->arch.tlb_addr, |
| 231 | gd->arch.tlb_addr + gd->arch.tlb_size); |
| 232 | |
| 233 | /* point TTBR to the new table */ |
| 234 | el = current_el(); |
| 235 | asm volatile("dsb sy"); |
| 236 | if (el == 1) { |
| 237 | asm volatile("msr ttbr0_el1, %0" |
| 238 | : : "r" ((u64)level0_table) : "memory"); |
| 239 | } else if (el == 2) { |
| 240 | asm volatile("msr ttbr0_el2, %0" |
| 241 | : : "r" ((u64)level0_table) : "memory"); |
| 242 | } else if (el == 3) { |
| 243 | asm volatile("msr ttbr0_el3, %0" |
| 244 | : : "r" ((u64)level0_table) : "memory"); |
| 245 | } else { |
| 246 | hang(); |
| 247 | } |
| 248 | asm volatile("isb"); |
| 249 | |
| 250 | /* |
| 251 | * MMU is already enabled, just need to invalidate TLB to load the |
| 252 | * new table. The new table is compatible with the current table, if |
| 253 | * MMU somehow walks through the new table before invalidation TLB, |
| 254 | * it still works. So we don't need to turn off MMU here. |
| 255 | */ |
| 256 | } |
| 257 | |
| 258 | int arch_cpu_init(void) |
| 259 | { |
| 260 | icache_enable(); |
| 261 | __asm_invalidate_dcache_all(); |
| 262 | __asm_invalidate_tlb_all(); |
| 263 | early_mmu_setup(); |
| 264 | set_sctlr(get_sctlr() | CR_C); |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | /* |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 269 | * This function is called from lib/board.c. |
| 270 | * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. |
| 271 | * There is no need to disable d-cache for this operation. |
| 272 | */ |
| 273 | void enable_caches(void) |
| 274 | { |
| 275 | final_mmu_setup(); |
| 276 | __asm_invalidate_tlb_all(); |
| 277 | } |
| 278 | #endif |
| 279 | |
| 280 | static inline u32 initiator_type(u32 cluster, int init_id) |
| 281 | { |
| 282 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 283 | u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; |
| 284 | u32 type = in_le32(&gur->tp_ityp[idx]); |
| 285 | |
| 286 | if (type & TP_ITYP_AV) |
| 287 | return type; |
| 288 | |
| 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | u32 cpu_mask(void) |
| 293 | { |
| 294 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 295 | int i = 0, count = 0; |
| 296 | u32 cluster, type, mask = 0; |
| 297 | |
| 298 | do { |
| 299 | int j; |
| 300 | cluster = in_le32(&gur->tp_cluster[i].lower); |
| 301 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
| 302 | type = initiator_type(cluster, j); |
| 303 | if (type) { |
| 304 | if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) |
| 305 | mask |= 1 << count; |
| 306 | count++; |
| 307 | } |
| 308 | } |
| 309 | i++; |
| 310 | } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); |
| 311 | |
| 312 | return mask; |
| 313 | } |
| 314 | |
| 315 | /* |
| 316 | * Return the number of cores on this SOC. |
| 317 | */ |
| 318 | int cpu_numcores(void) |
| 319 | { |
| 320 | return hweight32(cpu_mask()); |
| 321 | } |
| 322 | |
| 323 | int fsl_qoriq_core_to_cluster(unsigned int core) |
| 324 | { |
| 325 | struct ccsr_gur __iomem *gur = |
| 326 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 327 | int i = 0, count = 0; |
| 328 | u32 cluster; |
| 329 | |
| 330 | do { |
| 331 | int j; |
| 332 | cluster = in_le32(&gur->tp_cluster[i].lower); |
| 333 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
| 334 | if (initiator_type(cluster, j)) { |
| 335 | if (count == core) |
| 336 | return i; |
| 337 | count++; |
| 338 | } |
| 339 | } |
| 340 | i++; |
| 341 | } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); |
| 342 | |
| 343 | return -1; /* cannot identify the cluster */ |
| 344 | } |
| 345 | |
| 346 | u32 fsl_qoriq_core_to_type(unsigned int core) |
| 347 | { |
| 348 | struct ccsr_gur __iomem *gur = |
| 349 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 350 | int i = 0, count = 0; |
| 351 | u32 cluster, type; |
| 352 | |
| 353 | do { |
| 354 | int j; |
| 355 | cluster = in_le32(&gur->tp_cluster[i].lower); |
| 356 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
| 357 | type = initiator_type(cluster, j); |
| 358 | if (type) { |
| 359 | if (count == core) |
| 360 | return type; |
| 361 | count++; |
| 362 | } |
| 363 | } |
| 364 | i++; |
| 365 | } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); |
| 366 | |
| 367 | return -1; /* cannot identify the cluster */ |
| 368 | } |
| 369 | |
| 370 | #ifdef CONFIG_DISPLAY_CPUINFO |
| 371 | int print_cpuinfo(void) |
| 372 | { |
| 373 | struct sys_info sysinfo; |
| 374 | char buf[32]; |
| 375 | unsigned int i, core; |
| 376 | u32 type; |
| 377 | |
| 378 | get_sys_info(&sysinfo); |
| 379 | puts("Clock Configuration:"); |
| 380 | for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { |
| 381 | if (!(i % 3)) |
| 382 | puts("\n "); |
| 383 | type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); |
| 384 | printf("CPU%d(%s):%-4s MHz ", core, |
| 385 | type == TY_ITYP_VER_A7 ? "A7 " : |
| 386 | (type == TY_ITYP_VER_A53 ? "A53" : |
| 387 | (type == TY_ITYP_VER_A57 ? "A57" : " ")), |
| 388 | strmhz(buf, sysinfo.freq_processor[core])); |
| 389 | } |
| 390 | printf("\n Bus: %-4s MHz ", |
| 391 | strmhz(buf, sysinfo.freq_systembus)); |
| 392 | printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); |
York Sun | 1ecab78 | 2015-01-06 13:18:49 -0800 | [diff] [blame] | 393 | printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 394 | puts("\n"); |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | #endif |
J. German Rivera | 8ff14b7 | 2014-06-23 15:15:55 -0700 | [diff] [blame] | 399 | |
| 400 | int cpu_eth_init(bd_t *bis) |
| 401 | { |
| 402 | int error = 0; |
| 403 | |
| 404 | #ifdef CONFIG_FSL_MC_ENET |
Prabhakar Kushwaha | cfd9fbf | 2015-03-19 09:20:45 -0700 | [diff] [blame] | 405 | error = fsl_mc_ldpaa_init(bis); |
J. German Rivera | 8ff14b7 | 2014-06-23 15:15:55 -0700 | [diff] [blame] | 406 | #endif |
| 407 | return error; |
| 408 | } |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 409 | |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 410 | int arch_early_init_r(void) |
| 411 | { |
| 412 | int rv; |
| 413 | rv = fsl_lsch3_wake_seconday_cores(); |
| 414 | |
| 415 | if (rv) |
| 416 | printf("Did not wake secondary cores\n"); |
| 417 | |
| 418 | return 0; |
| 419 | } |
York Sun | 77a1097 | 2015-03-20 19:28:08 -0700 | [diff] [blame] | 420 | |
| 421 | int timer_init(void) |
| 422 | { |
| 423 | u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; |
| 424 | u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; |
| 425 | #ifdef COUNTER_FREQUENCY_REAL |
| 426 | unsigned long cntfrq = COUNTER_FREQUENCY_REAL; |
| 427 | |
| 428 | /* Update with accurate clock frequency */ |
| 429 | asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); |
| 430 | #endif |
| 431 | |
| 432 | /* Enable timebase for all clusters. |
| 433 | * It is safe to do so even some clusters are not enabled. |
| 434 | */ |
| 435 | out_le32(cltbenr, 0xf); |
| 436 | |
| 437 | /* Enable clock for timer |
| 438 | * This is a global setting. |
| 439 | */ |
| 440 | out_le32(cntcr, 0x1); |
| 441 | |
| 442 | return 0; |
| 443 | } |
pankaj chauhan | 6b99e7d | 2015-03-20 19:28:09 -0700 | [diff] [blame] | 444 | |
| 445 | void reset_cpu(ulong addr) |
| 446 | { |
| 447 | u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; |
| 448 | u32 val; |
| 449 | |
| 450 | /* Raise RESET_REQ_B */ |
| 451 | val = in_le32(rstcr); |
| 452 | val |= 0x02; |
| 453 | out_le32(rstcr, val); |
| 454 | } |