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git01.mediatek.com / filogic / uboot / f62397ac149b9afdfa7dd9d6b2b7ff390228d201 / . / arch / arm / dts / zynqmp-sc-vpk120-revB.dtso
blob: 750bc39139cc05aa8f8698347040a94b2a8a8b16 [file] [log] [blame]
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK120 revB
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12
13/dts-v1/;
14/plugin/;
15
16
17&{/} {
18 compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
19 "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
20};
21
22&i2c0 {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 tca6416_u233: gpio@20 { /* u233 */
27 compatible = "ti,tca6416";
28 reg = <0x20>;
29 gpio-controller; /* interrupt not connected */
30 #gpio-cells = <2>;
31 gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
32 "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
33 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
34 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
35 };
36
37 i2c-mux@74 { /* u33 */
38 compatible = "nxp,pca9548";
39 #address-cells = <1>;
40 #size-cells = <0>;
41 reg = <0x74>;
42 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
43 pmbus_i2c: i2c@0 {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 reg = <0>;
47 /* On connector J325 */
48 ir38060_41: regulator@41 { /* IR38060 - u259 */
49 compatible = "infineon,ir38060", "infineon,ir38064";
50 reg = <0x41>; /* i2c addr 0x11 */
51 };
52 ir38164_43: regulator@43 { /* IR38164 - u13 */
53 compatible = "infineon,ir38164";
54 reg = <0x43>; /* i2c addr 0x13 */
55 };
56 ir35221_46: pmic@46 { /* IR35221 - u152 */
57 compatible = "infineon,ir35221";
58 reg = <0x46>; /* i2c addr - 0x16 */
59 };
60 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
61 compatible = "infineon,irps5401";
62 reg = <0x47>; /* i2c addr 0x17 */
63 };
64 ir38164_49: regulator@49 { /* IR38164 - u189 */
65 compatible = "infineon,ir38164";
66 reg = <0x49>; /* i2c addr 0x19 */
67 };
68 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
69 compatible = "infineon,irps5401";
70 reg = <0x4c>; /* i2c addr 0x1c */
71 };
72 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
73 compatible = "infineon,irps5401";
74 reg = <0x4d>; /* i2c addr 0x1d */
75 };
76 ir38164_4e: regulator@4e { /* IR38164 - u185 */
77 compatible = "infineon,ir38164";
78 reg = <0x4e>; /* i2c addr 0x1e */
79 };
80 ir38164_4f: regulator@4f { /* IR38164 - u187 */
81 compatible = "infineon,ir38164";
82 reg = <0x4f>; /* i2c addr 0x1f */
83 };
84 };
85 pmbus1_ina226_i2c: i2c@1 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 reg = <1>;
89 /* FIXME check alerts coming to SC */
90 vccint: ina226@40 { /* u65 */
91 compatible = "ti,ina226";
92 reg = <0x40>;
93 shunt-resistor = <5000>;
94 };
95 vcc_soc: ina226@41 { /* u161 */
96 compatible = "ti,ina226";
97 reg = <0x41>;
98 shunt-resistor = <5000>;
99 };
100 vcc_pmc: ina226@42 { /* u163 */
101 compatible = "ti,ina226";
102 reg = <0x42>;
103 shunt-resistor = <5000>;
104 };
105 vcc_ram: ina226@43 { /* u5 */
106 compatible = "ti,ina226";
107 reg = <0x43>;
108 shunt-resistor = <5000>;
109 };
110 vcc_pslp: ina226@44 { /* u165 */
111 compatible = "ti,ina226";
112 reg = <0x44>;
113 shunt-resistor = <5000>;
114 };
115 vcc_psfp: ina226@45 { /* u164 */
116 compatible = "ti,ina226";
117 reg = <0x45>;
118 shunt-resistor = <5000>;
119 };
120 };
121 i2c@2 { /* NC */ /* FIXME maybe remove */
122 #address-cells = <1>;
123 #size-cells = <0>;
124 reg = <2>;
125 };
126 pmbus2_ina226_i2c: i2c@3 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 reg = <3>;
130 /* FIXME check alerts coming to SC */
131 vccaux: ina226@40 { /* u166 */
132 compatible = "ti,ina226";
133 reg = <0x40>;
134 shunt-resistor = <5000>;
135 };
136 vccaux_pmc: ina226@41 { /* u168 */
137 compatible = "ti,ina226";
138 reg = <0x41>;
139 shunt-resistor = <5000>;
140 };
141 mgtavcc: ina226@42 { /* u265 */
142 compatible = "ti,ina226";
143 reg = <0x42>;
144 shunt-resistor = <5000>;
145 };
146 vcc1v5: ina226@43 { /* u264 */
147 compatible = "ti,ina226";
148 reg = <0x43>;
149 shunt-resistor = <5000>;
150 };
151 vcco_mio: ina226@45 { /* u172 */
152 compatible = "ti,ina226";
153 reg = <0x45>;
154 shunt-resistor = <5000>;
155 };
156 mgtavtt: ina226@46 { /* u188 */
157 compatible = "ti,ina226";
158 reg = <0x46>;
159 shunt-resistor = <2000>;
160 };
161 vcco_502: ina226@47 { /* u174 */
162 compatible = "ti,ina226";
163 reg = <0x47>;
164 shunt-resistor = <5000>;
165 };
166 mgtvccaux: ina226@48 { /* u176 */
167 compatible = "ti,ina226";
168 reg = <0x48>;
169 shunt-resistor = <5000>;
170 };
171 vcc1v1_lp4: ina226@49 { /* u186 */
172 compatible = "ti,ina226";
173 reg = <0x49>;
174 shunt-resistor = <2000>;
175 };
176 vadj_fmc: ina226@4a { /* u184 */
177 compatible = "ti,ina226";
178 reg = <0x4a>;
179 shunt-resistor = <2000>;
180 };
181 lpdmgtyavcc: ina226@4b { /* u177 */
182 compatible = "ti,ina226";
183 reg = <0x4b>;
184 shunt-resistor = <5000>;
185 };
186 lpdmgtyavtt: ina226@4c { /* u260 */
187 compatible = "ti,ina226";
188 reg = <0x4c>;
189 shunt-resistor = <2000>;
190 };
191 lpdmgtyvccaux: ina226@4d { /* u234 */
192 compatible = "ti,ina226";
193 reg = <0x4d>;
194 shunt-resistor = <5000>;
195 };
196 };
197 i2c@4 { /* NC */
198 #address-cells = <1>;
199 #size-cells = <0>;
200 reg = <4>;
201 };
202 i2c@5 { /* NC */
203 #address-cells = <1>;
204 #size-cells = <0>;
205 reg = <5>;
206 };
207 user_si570: i2c@6 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 reg = <6>;
211 user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
212 #clock-cells = <0>;
213 compatible = "silabs,si570";
214 reg = <0x5f>;
215 temperature-stability = <50>;
216 factory-fout = <100000000>;
217 clock-frequency = <100000000>;
218 clock-output-names = "fmc_si570";
219 silabs,skip-recall;
220 };
221
222 };
223 /* 7 unused */
224 };
225};
226
227&i2c1 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230
231 i2c-mux@74 { /* u35 */
232 compatible = "nxp,pca9548";
233 #address-cells = <1>;
234 #size-cells = <0>;
235 reg = <0x74>;
236 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
237 ref_clk_i2c: i2c@0 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 reg = <0>;
241 ref_clk: clock-generator@5d { /* u32 */
242 #clock-cells = <0>;
243 compatible = "silabs,si570";
244 reg = <0x5d>;
245 temperature-stability = <50>;
246 factory-fout = <33333333>;
247 clock-frequency = <33333333>;
248 clock-output-names = "ref_clk";
249 silabs,skip-recall;
250 };
251 };
252 fmcp1_i2c: i2c@1 {
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg = <1>;
256 /* FIXME connection to Samtec J51C */
257 /* expected eeprom 0x50 SE cards */
258 };
259 i2c@2 { /* NC - FIXME */
260 #address-cells = <1>;
261 #size-cells = <0>;
262 reg = <2>;
263 };
264 lpddr4_si570_clk3_i2c: i2c@3 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 reg = <3>;
268 lpddr4_clk3: clock-generator@60 { /* u4 */
269 #clock-cells = <0>;
270 compatible = "silabs,si570";
271 reg = <0x60>;
272 temperature-stability = <50>;
273 factory-fout = <200000000>;
274 clock-frequency = <200000000>;
275 clock-output-names = "lpddr4_clk3";
276 silabs,skip-recall;
277 };
278 };
279 lpddr4_si570_clk2_i2c: i2c@4 {
280 #address-cells = <1>;
281 #size-cells = <0>;
282 reg = <4>;
283 lpddr4_clk2: clock-generator@60 { /* u3 */
284 #clock-cells = <0>;
285 compatible = "silabs,si570";
286 reg = <0x60>;
287 temperature-stability = <50>;
288 factory-fout = <200000000>;
289 clock-frequency = <200000000>;
290 clock-output-names = "lpddr4_clk2";
291 silabs,skip-recall;
292 };
293 };
294 lpddr4_si570_clk1_i2c: i2c@5 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 reg = <5>;
298 lpddr4_clk1: clock-generator@60 { /* u248 */
299 #clock-cells = <0>;
300 compatible = "silabs,si570";
301 reg = <0x60>;
302 temperature-stability = <50>;
303 factory-fout = <200000000>;
304 clock-frequency = <200000000>;
305 clock-output-names = "lpddr4_clk1";
306 silabs,skip-recall;
307 };
308 };
309 qsfpdd_i2c: i2c@6 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <6>;
313 /* J1/J2 connectors */
314 };
315 idt8a34001_i2c: i2c@7 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <7>;
319 /* Via J310 connector */
320 idt_8a34001: phc@5b {
321 compatible = "idt,8a34001"; /* u219B */
322 reg = <0x5b>; /* FIXME not in schematics */
323 };
324 };
325 };
326};