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git01.mediatek.com / filogic / uboot / f62361523685ec6b85d9f3e83d6e08960993fa92 / . / board / ttcontrol / vision2 / imximage_hynix.cfg
blob: c1de94fa13932cdf7f2456c96717c34672084e88 [file] [log] [blame]
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]1/*
2 * (C) Copyright 2009
3 * Stefano Babic DENX Software Engineering sbabic@denx.de.
4 *
5 * (C) Copyright 2010
6 * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not write to the Free Software
23 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
24 * MA 02110-1301 USA
25 *
26 * Refer docs/README.imxmage for more details about how-to configure
27 * and create imximage boot image
28 *
29 * The syntax is taken as close as possible with the kwbimage
30 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]31
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]32/*
33 * Boot Device : one of
34 * spi, nand, onenand, sd
35 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]36BOOT_FROM spi
37
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]38/*
39 * Device Configuration Data (DCD)
40 *
41 * Each entry must have the format:
42 * Addr-type Address Value
43 *
44 * where:
45 * Addr-type register length (1,2 or 4 bytes)
46 * Address absolute address of the register
47 * value value to be stored in the register
48 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]49
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]50/*
51 * #######################
52 * ### Disable WDOG ###
53 * #######################
54 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]55DATA 2 0x73f98000 0x30
56
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]57/*
58 * #######################
59 * ### SET DDR Clk ###
60 * #######################
61 */
62/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]63DATA 4 0x73FD4018 0x000024C0
64
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]65/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]66DATA 4 0x73FD4038 0x2010241
67
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]68/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]69DATA 4 0x73fa8600 0x00000107
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]70/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]71DATA 4 0x73fa8604 0x00000107
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]72/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]73DATA 4 0x73fa8608 0x00000187
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]74/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]75DATA 4 0x73fa860c 0x00000187
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]76/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]77DATA 4 0x73fa8614 0x00000107
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]78/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]79DATA 4 0x73fa86a8 0x00000187
80
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]81/*
82 * #######################
83 * ### Settings IOMUXC ###
84 * #######################
85 */
86/*
87 * DDR IOMUX configuration
88 * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
89 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
90 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]91DATA 4 0x73fa84b8 0x000000e7
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]92/* PVTC MAX (at GPC, PGR reg) */
93/* DATA 4 0x73FD8004 0x1fc00000 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]94
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]95/* DQM0 DS high slew rate slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]96DATA 4 0x73fa84d4 0x000000e4
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]97/* DQM1 DS high slew rate slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]98DATA 4 0x73fa84d8 0x000000e4
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]99/* DQM2 DS high slew rate slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]100DATA 4 0x73fa84dc 0x000000e4
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]101/* DQM3 DS high slew rate slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]102DATA 4 0x73fa84e0 0x000000e4
103
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]104/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]105DATA 4 0x73fa84bc 0x000000c4
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]106/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]107DATA 4 0x73fa84c0 0x000000c4
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]108/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]109DATA 4 0x73fa84c4 0x000000c4
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]110/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]111DATA 4 0x73fa84c8 0x000000c4
112
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]113/* DRAM_DATA B0 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]114DATA 4 0x73fa88a4 0x00000004
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]115/* DRAM_DATA B1 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]116DATA 4 0x73fa88ac 0x00000004
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]117/* DRAM_DATA B2 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]118DATA 4 0x73fa88b8 0x00000004
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]119/* DRAM_DATA B3 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]120DATA 4 0x73fa882c 0x00000004
121
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]122/* DRAM_DATA B0 slew rate */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]123DATA 4 0x73fa8878 0x00000000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]124/* DRAM_DATA B1 slew rate */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]125DATA 4 0x73fa8880 0x00000000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]126/* DRAM_DATA B2 slew rate */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]127DATA 4 0x73fa888c 0x00000000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]128/* DRAM_DATA B3 slew rate */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]129DATA 4 0x73fa889c 0x00000000
130
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]131/*
132 * #######################
133 * ### Configure SDRAM ###
134 * #######################
135 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]136
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]137/* Configure CS0 */
138/* ####################### */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]139
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]140/* ESDCTL0: Enable controller */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]141DATA 4 0x83fd9000 0x83220000
142
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]143/* Init DRAM on CS0 /
144/* ESDSCR: Precharge command */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]145DATA 4 0x83fd9014 0x04008008
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]146/* ESDSCR: Refresh command */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]147DATA 4 0x83fd9014 0x00008010
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]148/* ESDSCR: Refresh command */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]149DATA 4 0x83fd9014 0x00008010
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]150/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]151DATA 4 0x83fd9014 0x00338018
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]152/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]153DATA 4 0x83fd9014 0x0020801a
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]154/* ESDSCR */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]155DATA 4 0x83fd9014 0x00008000
156
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]157/* ESDSCR: EMR with full Drive strength */
158/* DATA 4 0x83fd9014 0x0000801a */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]159
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]160/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]161DATA 4 0x83fd9000 0xC3220000
162
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]163/*
164 * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
165 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
166 * DATA 4 0x83fd9004 0xC33574AA
167 */
168/*
169 * micron mDDR
170 * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
171 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
172 * DATA 4 0x83FD9004 0x101564a8
173 */
174/*
175 * hynix mDDR
176 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
177 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
178 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]179DATA 4 0x83FD9004 0x704564a8
180
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]181/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]182DATA 4 0x83fd9010 0x000a1700
183
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]184/* Configure CS1 */
185/* ####################### */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]186
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]187/* ESDCTL1: Enable controller */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]188DATA 4 0x83fd9008 0x83220000
189
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]190/* Init DRAM on CS1 */
191/* ESDSCR: Precharge command */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]192DATA 4 0x83fd9014 0x0400800c
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]193/* ESDSCR: Refresh command */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]194DATA 4 0x83fd9014 0x00008014
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]195/* ESDSCR: Refresh command */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]196DATA 4 0x83fd9014 0x00008014
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]197/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]198DATA 4 0x83fd9014 0x0033801c
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]199/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]200DATA 4 0x83fd9014 0x0020801e
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]201/* ESDSCR */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]202DATA 4 0x83fd9014 0x00008004
203
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]204/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]205DATA 4 0x83fd9008 0xC3220000
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]206/*
207 * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
208 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
209 * DATA 4 0x83fd900c 0xC33574AA
210 */
211/*
212 * micron mDDR
213 * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
214 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
215 * DATA 4 0x83FD900C 0x101564a8
216 */
217/*
218 * hynix mDDR
219 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
220 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
221 */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]222DATA 4 0x83FD900C 0x704564a8
223
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]224/* ESDSCR (mDRAM configuration finished) */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]225DATA 4 0x83FD9014 0x00000004
226
Troy Kiskya18d7862013-01-18 16:14:24 +0000[diff] [blame]227/* ESDSCR - clear "configuration request" bit */
Stefano Babice1b6f592010-07-06 19:32:09 +0200[diff] [blame]228DATA 4 0x83fd9014 0x00000000