blob: 2aab463a90fc06ed12d6d1d4a30ce58ee9aa1eb7 [file] [log] [blame]
TsiChungLiew2e0aeef2007-07-05 22:39:07 -05001/*
2 * ColdFire Internal Memory Map and Defines
3 *
Alison Wangfdc2fb12012-10-18 19:25:51 +00004 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChungLiew2e0aeef2007-07-05 22:39:07 -05005 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __IMMAP_H
27#define __IMMAP_H
Stefan Roesef1110122007-07-16 13:11:12 +020028
TsiChung Liewb354aef2009-06-12 11:29:00 +000029#if defined(CONFIG_MCF520x)
30#include <asm/immap_520x.h>
31#include <asm/m520x.h>
32
33#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
34#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
35
36/* Timer */
37#ifdef CONFIG_MCFTMR
38#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
39#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
40#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
41#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
42#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
43#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
44#define CONFIG_SYS_TMRINTR_PRI (6)
45#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
46#endif
47
48#ifdef CONFIG_MCFPIT
49#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
50#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
51#define CONFIG_SYS_PIT_PRESCALE (6)
52#endif
53
54#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
55#define CONFIG_SYS_NUM_IRQS (128)
56#endif /* CONFIG_M520x */
57
TsiChungLiew99b037a2008-01-14 17:43:33 -060058#ifdef CONFIG_M52277
59#include <asm/immap_5227x.h>
60#include <asm/m5227x.h>
61
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
TsiChungLiew99b037a2008-01-14 17:43:33 -060063
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiew99b037a2008-01-14 17:43:33 -060065
66#ifdef CONFIG_LCD
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_LCD_BASE (MMAP_LCD)
TsiChungLiew99b037a2008-01-14 17:43:33 -060068#endif
69
70/* Timer */
71#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
73#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
74#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
75#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
76#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
77#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
78#define CONFIG_SYS_TMRINTR_PRI (6)
79#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew99b037a2008-01-14 17:43:33 -060080#endif
81
82#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
84#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
85#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiew99b037a2008-01-14 17:43:33 -060086#endif
87
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
89#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew99b037a2008-01-14 17:43:33 -060090#endif /* CONFIG_M52277 */
91
TsiChungLiewb859ef12007-08-16 19:23:50 -050092#ifdef CONFIG_M5235
93#include <asm/immap_5235.h>
94#include <asm/m5235.h>
95
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
97#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiewb859ef12007-08-16 19:23:50 -050098
99/* Timer */
100#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
102#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
103#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
104#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
105#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
106#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
107#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
108#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500109#endif
110
111#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
113#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
114#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500115#endif
116
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
118#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500119#endif /* CONFIG_M5235 */
120
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500121#ifdef CONFIG_M5249
122#include <asm/immap_5249.h>
123#include <asm/m5249.h>
124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
128#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500129
130/* Timer */
131#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
133#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
134#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
135#define CONFIG_SYS_TMRINTR_NO (31)
136#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
137#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
138#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
139#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500140#endif
141#endif /* CONFIG_M5249 */
142
TsiChungLiew34674692007-08-16 13:20:50 -0500143#ifdef CONFIG_M5253
144#include <asm/immap_5253.h>
145#include <asm/m5249.h>
146#include <asm/m5253.h>
147
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew34674692007-08-16 13:20:50 -0500149
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
151#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew34674692007-08-16 13:20:50 -0500152
153/* Timer */
154#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
156#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
157#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
158#define CONFIG_SYS_TMRINTR_NO (27)
159#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
160#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
161#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
162#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew34674692007-08-16 13:20:50 -0500163#endif
164#endif /* CONFIG_M5253 */
165
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500166#ifdef CONFIG_M5271
167#include <asm/immap_5271.h>
168#include <asm/m5271.h>
169
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
171#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500172
173/* Timer */
174#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
176#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
177#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
178#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
179#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
180#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
Richard Retanubun0dd94312009-03-26 15:26:01 -0400181#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500183#endif
184
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
186#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500187#endif /* CONFIG_M5271 */
188
189#ifdef CONFIG_M5272
190#include <asm/immap_5272.h>
191#include <asm/m5272.h>
192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
194#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
197#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500198
199/* Timer */
200#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
202#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
203#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
204#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
205#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
206#define CONFIG_SYS_TMRINTR_PEND (0)
207#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
208#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500209#endif
210#endif /* CONFIG_M5272 */
211
Matthew Fettke761e2e92008-02-04 15:38:20 -0600212#ifdef CONFIG_M5275
213#include <asm/immap_5275.h>
214#include <asm/m5275.h>
215
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
217#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
218#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
Matthew Fettke761e2e92008-02-04 15:38:20 -0600219
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
221#define CONFIG_SYS_NUM_IRQS (192)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600222
223/* Timer */
224#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
226#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
227#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
228#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
229#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
230#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
231#define CONFIG_SYS_TMRINTR_PRI (0x1E)
232#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600233#endif
234#endif /* CONFIG_M5275 */
235
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500236#ifdef CONFIG_M5282
237#include <asm/immap_5282.h>
238#include <asm/m5282.h>
239
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
241#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500242
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
244#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500245
246/* Timer */
247#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
249#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
250#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
251#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
252#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
253#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
254#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
255#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500256#endif
257#endif /* CONFIG_M5282 */
258
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000259#if defined(CONFIG_MCF5301x)
260#include <asm/immap_5301x.h>
261#include <asm/m5301x.h>
262
263#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
264#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
265#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
266
267#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
268
269/* Timer */
270#ifdef CONFIG_MCFTMR
271#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
272#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
273#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
274#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
275#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
276#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
277#define CONFIG_SYS_TMRINTR_PRI (6)
278#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
279#endif
280
281#ifdef CONFIG_MCFPIT
282#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
283#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
284#define CONFIG_SYS_PIT_PRESCALE (6)
285#endif
286
287#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
288#define CONFIG_SYS_NUM_IRQS (128)
289#endif /* CONFIG_M5301x */
290
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600291#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500292#include <asm/immap_5329.h>
293#include <asm/m5329.h>
294
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
296#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
297#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500298
299/* Timer */
300#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
302#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
303#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
304#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
305#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
306#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
307#define CONFIG_SYS_TMRINTR_PRI (6)
308#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500309#endif
310
311#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
313#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
314#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500315#endif
316
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
318#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600319#endif /* CONFIG_M5329 && CONFIG_M5373 */
Stefan Roesef1110122007-07-16 13:11:12 +0200320
Alison Wangfdc2fb12012-10-18 19:25:51 +0000321#if defined(CONFIG_M54418)
322#include <asm/immap_5441x.h>
323#include <asm/m5441x.h>
324
325#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
326#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
327
328#if (CONFIG_SYS_UART_PORT < 4)
329#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
330 (CONFIG_SYS_UART_PORT * 0x4000))
331#else
332#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
333 ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
334#endif
335
336#define MMAP_DSPI MMAP_DSPI0
337#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
338
339/* Timer */
340#ifdef CONFIG_MCFTMR
341#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
342#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
343#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
344#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
345#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
346#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
347#define CONFIG_SYS_TMRINTR_PRI (6)
348#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
349#endif
350
351#ifdef CONFIG_MCFPIT
352#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
353#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
354#define CONFIG_SYS_PIT_PRESCALE (6)
355#endif
356
357#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
358#define CONFIG_SYS_NUM_IRQS (128)
359
360#endif /* CONFIG_M54418 */
361
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000362#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500363#include <asm/immap_5445x.h>
364#include <asm/m5445x.h>
365
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200366#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000367#if defined(CONFIG_M54455EVB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000369#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500370
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200371#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500372
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200373#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500374
375/* Timer */
376#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200377#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
378#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
379#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
380#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
381#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
382#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
383#define CONFIG_SYS_TMRINTR_PRI (6)
384#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500385#endif
386
387#ifdef CONFIG_MCFPIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200388#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
389#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
390#define CONFIG_SYS_PIT_PRESCALE (6)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500391#endif
392
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200393#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
394#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500395
396#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200397#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
398#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
399#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
400#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500401#endif
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000402#endif /* CONFIG_M54451 || CONFIG_M54455 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500403
TsiChungLiew471b2c62008-01-15 13:39:44 -0600404#ifdef CONFIG_M547x
405#include <asm/immap_547x_8x.h>
406#include <asm/m547x_8x.h>
407
408#ifdef CONFIG_FSLDMAFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200409#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
410#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600411
412#define FEC0_RX_TASK 0
413#define FEC0_TX_TASK 1
414#define FEC0_RX_PRIORITY 6
415#define FEC0_TX_PRIORITY 7
416#define FEC0_RX_INIT 16
417#define FEC0_TX_INIT 17
418#define FEC1_RX_TASK 2
419#define FEC1_TX_TASK 3
420#define FEC1_RX_PRIORITY 6
421#define FEC1_TX_PRIORITY 7
422#define FEC1_RX_INIT 30
423#define FEC1_TX_INIT 31
424#endif
425
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200426#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600427
428#ifdef CONFIG_SLTTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200429#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
430#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
431#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
432#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
433#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
434#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
435#define CONFIG_SYS_TMRINTR_PRI (0x1E)
436#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600437#endif
438
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200439#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
440#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600441
442#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200443#define CONFIG_SYS_PCI_BAR0 (0x40000000)
444#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
445#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
446#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600447#endif
448#endif /* CONFIG_M547x */
449
450#ifdef CONFIG_M548x
451#include <asm/immap_547x_8x.h>
452#include <asm/m547x_8x.h>
453
454#ifdef CONFIG_FSLDMAFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200455#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
456#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600457
458#define FEC0_RX_TASK 0
459#define FEC0_TX_TASK 1
460#define FEC0_RX_PRIORITY 6
461#define FEC0_TX_PRIORITY 7
462#define FEC0_RX_INIT 16
463#define FEC0_TX_INIT 17
464#define FEC1_RX_TASK 2
465#define FEC1_TX_TASK 3
466#define FEC1_RX_PRIORITY 6
467#define FEC1_TX_PRIORITY 7
468#define FEC1_RX_INIT 30
469#define FEC1_TX_INIT 31
470#endif
471
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200472#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600473
474/* Timer */
475#ifdef CONFIG_SLTTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200476#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
477#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
478#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
479#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
480#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
481#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
482#define CONFIG_SYS_TMRINTR_PRI (0x1E)
483#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600484#endif
485
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200486#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
487#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600488
489#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200490#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
491#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
492#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
493#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600494#endif
495#endif /* CONFIG_M548x */
496
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500497#endif /* __IMMAP_H */