Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010, Stefano Babic <sbabic@denx.de> |
| 4 | * |
| 5 | * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. |
| 6 | * |
| 7 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> |
| 8 | * |
| 9 | * Configuration for the MX35pdk Freescale board. |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | #include <asm/arch/imx-regs.h> |
| 16 | |
| 17 | /* High Level Configuration Options */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 18 | #define CONFIG_MX35 |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 19 | |
Gong Qianyu | 52de2e5 | 2015-10-26 19:47:42 +0800 | [diff] [blame] | 20 | #define CONFIG_SYS_FSL_CLK |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 21 | |
| 22 | /* Set TEXT at the beginning of the NOR flash */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 23 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 24 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 25 | #define CONFIG_REVISION_TAG |
| 26 | #define CONFIG_SETUP_MEMORY_TAGS |
| 27 | #define CONFIG_INITRD_TAG |
| 28 | |
| 29 | /* |
| 30 | * Size of malloc() pool |
| 31 | */ |
| 32 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) |
| 33 | |
| 34 | /* |
| 35 | * Hardware drivers |
| 36 | */ |
trem | 0399741 | 2013-09-21 18:13:36 +0200 | [diff] [blame] | 37 | #define CONFIG_SYS_I2C |
| 38 | #define CONFIG_SYS_I2C_MXC |
Albert ARIBAUD \\(3ADEV\\) | eb94387 | 2015-09-21 22:43:38 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 40 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
York Sun | f1a5216 | 2015-03-20 10:20:40 -0700 | [diff] [blame] | 41 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 42 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 43 | /* |
| 44 | * PMIC Configs |
| 45 | */ |
Łukasz Majewski | 1b6d9ed | 2012-11-13 03:22:14 +0000 | [diff] [blame] | 46 | #define CONFIG_POWER |
| 47 | #define CONFIG_POWER_I2C |
| 48 | #define CONFIG_POWER_FSL |
Simon Glass | 0222981 | 2014-05-20 06:01:34 -0600 | [diff] [blame] | 49 | #define CONFIG_POWER_FSL_MC13892 |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 50 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 |
Fabio Estevam | 69517dc | 2011-10-25 01:35:37 +0000 | [diff] [blame] | 51 | #define CONFIG_RTC_MC13XXX |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 52 | |
| 53 | /* |
| 54 | * MFD MC9SDZ60 |
| 55 | */ |
| 56 | #define CONFIG_FSL_MC9SDZ60 |
| 57 | #define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 |
| 58 | |
| 59 | /* |
| 60 | * UART (console) |
| 61 | */ |
| 62 | #define CONFIG_MXC_UART |
Stefano Babic | 1ca47d9 | 2011-11-22 15:22:39 +0100 | [diff] [blame] | 63 | #define CONFIG_MXC_UART_BASE UART1_BASE |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 64 | |
| 65 | /* allow to overwrite serial and ethaddr */ |
| 66 | #define CONFIG_ENV_OVERWRITE |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Command definition |
| 70 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 71 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 72 | #define CONFIG_NET_RETRY_COUNT 100 |
| 73 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 74 | |
| 75 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ |
| 76 | |
| 77 | /* |
| 78 | * Ethernet on the debug board (SMC911) |
| 79 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 80 | #define CONFIG_HAS_ETH1 |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 81 | #define CONFIG_ETHPRIME |
| 82 | |
| 83 | /* |
| 84 | * Ethernet on SOC (FEC) |
| 85 | */ |
| 86 | #define CONFIG_FEC_MXC |
| 87 | #define IMX_FEC_BASE FEC_BASE_ADDR |
| 88 | #define CONFIG_FEC_MXC_PHYADDR 0x1F |
| 89 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 90 | #define CONFIG_ARP_TIMEOUT 200UL |
| 91 | |
| 92 | /* |
| 93 | * Miscellaneous configurable options |
| 94 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 95 | |
| 96 | #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ |
| 97 | #define CONFIG_SYS_MEMTEST_END 0x10000 |
| 98 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 99 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 100 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 101 | /* |
| 102 | * Physical Memory Map |
| 103 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 104 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
| 105 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) |
Stefano Babic | 19edc94 | 2011-08-02 14:42:36 +0200 | [diff] [blame] | 106 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR |
| 107 | #define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 108 | |
| 109 | #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR |
| 110 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) |
| 111 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) |
| 112 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 113 | GENERATED_GBL_DATA_SIZE) |
| 114 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 115 | CONFIG_SYS_GBL_DATA_OFFSET) |
| 116 | |
| 117 | /* |
| 118 | * MTD Command for mtdparts |
| 119 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 120 | |
| 121 | /* |
| 122 | * FLASH and environment organization |
| 123 | */ |
| 124 | #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR |
| 125 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 126 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
| 127 | /* Monitor at beginning of flash */ |
| 128 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 129 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| 130 | |
| 131 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 132 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
| 133 | |
| 134 | /* Address and size of Redundant Environment Sector */ |
| 135 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
| 136 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
| 137 | |
| 138 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
| 139 | CONFIG_SYS_MONITOR_LEN) |
| 140 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 141 | #if defined(CONFIG_FSL_ENV_IN_NAND) |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 142 | #define CONFIG_ENV_OFFSET (1024 * 1024) |
| 143 | #endif |
| 144 | |
| 145 | /* |
| 146 | * CFI FLASH driver setup |
| 147 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 148 | |
| 149 | /* A non-standard buffered write algorithm */ |
| 150 | #define CONFIG_FLASH_SPANSION_S29WS_N |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 151 | |
| 152 | /* |
| 153 | * NAND FLASH driver setup |
| 154 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 155 | #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) |
| 156 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 157 | #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) |
| 158 | #define CONFIG_MXC_NAND_HWECC |
| 159 | #define CONFIG_SYS_NAND_LARGEPAGE |
| 160 | |
Benoît Thébaudeau | 50af5db | 2012-11-13 09:58:25 +0000 | [diff] [blame] | 161 | /* EHCI driver */ |
Benoît Thébaudeau | 50af5db | 2012-11-13 09:58:25 +0000 | [diff] [blame] | 162 | #define CONFIG_EHCI_IS_TDI |
| 163 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 164 | #define CONFIG_USB_EHCI_MXC |
| 165 | #define CONFIG_MXC_USB_PORT 0 |
| 166 | #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \ |
| 167 | MXC_EHCI_POWER_PINS_ENABLED | \ |
| 168 | MXC_EHCI_OC_PIN_ACTIVE_LOW) |
| 169 | #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI) |
| 170 | |
Stefano Babic | 9dd9d0f | 2012-09-05 21:47:42 +0000 | [diff] [blame] | 171 | /* mmc driver */ |
Stefano Babic | 9dd9d0f | 2012-09-05 21:47:42 +0000 | [diff] [blame] | 172 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| 173 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 |
| 174 | |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 175 | /* |
| 176 | * Default environment and default scripts |
| 177 | * to update uboot and load kernel |
| 178 | */ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 179 | |
| 180 | #define CONFIG_HOSTNAME "mx35pdk" |
| 181 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 182 | "netdev=eth1\0" \ |
| 183 | "ethprime=smc911x\0" \ |
| 184 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 185 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 186 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 187 | "addip_sta=setenv bootargs ${bootargs} " \ |
| 188 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 189 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 190 | "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ |
| 191 | "addip=if test -n ${ipdyn};then run addip_dyn;" \ |
Marek Vasut | fd5ba89 | 2012-09-23 17:41:23 +0200 | [diff] [blame] | 192 | "else run addip_sta;fi\0" \ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 193 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
| 194 | "addtty=setenv bootargs ${bootargs}" \ |
| 195 | " console=ttymxc0,${baudrate}\0" \ |
| 196 | "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ |
| 197 | "loadaddr=80800000\0" \ |
| 198 | "kernel_addr_r=80800000\0" \ |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 199 | "hostname=" CONFIG_HOSTNAME "\0" \ |
| 200 | "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ |
| 201 | "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 202 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
| 203 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 204 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ |
| 205 | "bootm ${kernel_addr}\0" \ |
| 206 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ |
| 207 | "run nfsargs addip addtty addmtd addmisc;" \ |
| 208 | "bootm ${kernel_addr_r}\0" \ |
| 209 | "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ |
| 210 | "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 211 | "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 212 | "load=tftp ${loadaddr} ${u-boot}\0" \ |
Marek Vasut | fd5ba89 | 2012-09-23 17:41:23 +0200 | [diff] [blame] | 213 | "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
Stefano Babic | 9dd9d0f | 2012-09-05 21:47:42 +0000 | [diff] [blame] | 214 | "update=protect off ${uboot_addr} +80000;" \ |
| 215 | "erase ${uboot_addr} +80000;" \ |
Stefano Babic | f02e697 | 2011-01-20 08:05:15 +0000 | [diff] [blame] | 216 | "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ |
| 217 | "upd=if run load;then echo Updating u-boot;if run update;" \ |
| 218 | "then echo U-Boot updated;" \ |
| 219 | "else echo Error updating u-boot !;" \ |
| 220 | "echo Board without bootloader !!;" \ |
| 221 | "fi;" \ |
| 222 | "else echo U-Boot not downloaded..exiting;fi\0" \ |
| 223 | "bootcmd=run net_nfs\0" |
| 224 | |
| 225 | #endif /* __CONFIG_H */ |