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git01.mediatek.com / filogic / uboot / f5ff42940083ecb6c281ac13f72640213813373c / . / arch / powerpc / cpu / 74xx_7xx / kgdb.S
blob: 42b3a76009c21ac36b69930d7d40438dcccc8e16 [file] [log] [blame]
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]1/*
2 * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]5 */
6
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]7#include <config.h>
8#include <command.h>
9#include <74xx_7xx.h>
10#include <version.h>
11
12#include <ppc_asm.tmpl>
13#include <ppc_defs.h>
14
15#include <asm/cache.h>
16#include <asm/mmu.h>
17
Jon Loeligera5217742007-07-09 18:57:22 -0500[diff] [blame]18#if defined(CONFIG_CMD_KGDB)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]19
20 /*
21 * cache flushing routines for kgdb
22 */
23
24 .globl kgdb_flush_cache_all
25kgdb_flush_cache_all:
wdenk99651602004-09-28 21:39:45 +0000[diff] [blame]26 lis r3,0
27 addis r4,r0,0x0040
28kgdb_flush_loop:
29 lwz r5,0(r3)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]30 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenk99651602004-09-28 21:39:45 +0000[diff] [blame]31 cmp 0,0,r3,r4
32 bne kgdb_flush_loop
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]33 SYNC
wdenk99651602004-09-28 21:39:45 +0000[diff] [blame]34 mfspr r3,1008
35 ori r3,r3,0x8800
36 mtspr 1008,r3
37 sync
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]38 blr
39
40 .globl kgdb_flush_cache_range
41kgdb_flush_cache_range:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]42 li r5,CONFIG_SYS_CACHELINE_SIZE-1
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]43 andc r3,r3,r5
44 subf r4,r3,r4
45 add r4,r4,r5
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]46 srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]47 beqlr
48 mtctr r4
49 mr r6,r3
501: dcbst 0,r3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]51 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]52 bdnz 1b
53 sync /* wait for dcbst's to get to ram */
54 mtctr r4
552: icbi 0,r6
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]56 addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]57 bdnz 2b
58 SYNC
59 blr
60
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500[diff] [blame]61#endif