Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * LPC32xx MUX interface |
| 3 | * |
| 4 | * (C) Copyright 2015 DENX Software Engineering GmbH |
| 5 | * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | /** |
| 11 | * MUX register map for LPC32xx |
| 12 | */ |
| 13 | |
| 14 | struct mux_regs { |
Sylvain Lemieux | da09677 | 2015-07-27 13:37:34 -0400 | [diff] [blame] | 15 | u32 reserved1[10]; |
| 16 | u32 p2_mux_set; |
| 17 | u32 p2_mux_clr; |
| 18 | u32 p2_mux_state; |
| 19 | u32 reserved2[51]; |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 20 | u32 p_mux_set; |
| 21 | u32 p_mux_clr; |
| 22 | u32 p_mux_state; |
Sylvain Lemieux | da09677 | 2015-07-27 13:37:34 -0400 | [diff] [blame] | 23 | u32 reserved3; |
| 24 | u32 p3_mux_set; |
| 25 | u32 p3_mux_clr; |
| 26 | u32 p3_mux_state; |
| 27 | u32 reserved4; |
| 28 | u32 p0_mux_set; |
| 29 | u32 p0_mux_clr; |
| 30 | u32 p0_mux_state; |
| 31 | u32 reserved5; |
| 32 | u32 p1_mux_set; |
| 33 | u32 p1_mux_clr; |
| 34 | u32 p1_mux_state; |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 35 | }; |