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git01.mediatek.com / filogic / uboot / f5c208de9784aac2797a3436ad205ff14b796d57 / . / arch / arm / cpu / arm926ejs / mx27 / reset.c
blob: e2437d13c84f77659602e84a6f6c59809ebb69ba [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Ilya Yanok416a41f2009-06-08 04:12:45 +0400[diff] [blame]2/*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
10 *
11 * (C) Copyright 2002
12 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
13 *
14 * (C) Copyright 2009
15 * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
Ilya Yanok416a41f2009-06-08 04:12:45 +0400[diff] [blame]16 */
17
18#include <common.h>
19#include <asm/io.h>
20#include <asm/arch/imx-regs.h>
21
22/*
23 * Reset the cpu by setting up the watchdog timer and let it time out
24 */
Fabio Estevamf231efb2011-10-13 05:34:59 +0000[diff] [blame]25void reset_cpu(ulong ignored)
Ilya Yanok416a41f2009-06-08 04:12:45 +0400[diff] [blame]26{
27 struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
28 /* Disable watchdog and set Time-Out field to 0 */
Leonid Iziumtsev3056e502016-03-20 14:10:55 +0100[diff] [blame]29 writew(0x0000, &regs->wcr);
Ilya Yanok416a41f2009-06-08 04:12:45 +0400[diff] [blame]30
31 /* Write Service Sequence */
Leonid Iziumtsev3056e502016-03-20 14:10:55 +0100[diff] [blame]32 writew(0x5555, &regs->wsr);
33 writew(0xAAAA, &regs->wsr);
Ilya Yanok416a41f2009-06-08 04:12:45 +0400[diff] [blame]34
35 /* Enable watchdog */
Leonid Iziumtsev3056e502016-03-20 14:10:55 +0100[diff] [blame]36 writew(WCR_WDE, &regs->wcr);
Ilya Yanok416a41f2009-06-08 04:12:45 +0400[diff] [blame]37
38 while (1);
39 /*NOTREACHED*/
40}