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git01.mediatek.com / filogic / uboot / f5bea566893b3d5c0b89e40cfb9bffc69c6ef334 / . / test / dm / dma.c
blob: be3862963b18ae74a33a866b680b915ccff19cc2 [file] [log] [blame]
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Direct Memory Access U-Class tests
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated <www.ti.com>
6 * Grygorii Strashko <grygorii.strashko@ti.com>
7 */
8
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]9#include <dm.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]10#include <malloc.h>
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]11#include <dm/test.h>
12#include <dma.h>
Simon Glass75c4d412020-07-19 10:15:37 -0600[diff] [blame]13#include <test/test.h>
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]14#include <test/ut.h>
15
16static int dm_test_dma_m2m(struct unit_test_state *uts)
17{
18 struct udevice *dev;
19 struct dma dma_m2m;
20 u8 src_buf[512];
21 u8 dst_buf[512];
22 size_t len = 512;
23 int i;
24
25 ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
26 ut_assertok(dma_get_by_name(dev, "m2m", &dma_m2m));
27
28 memset(dst_buf, 0, len);
29 for (i = 0; i < len; i++)
30 src_buf[i] = i;
31
32 ut_assertok(dma_memcpy(dst_buf, src_buf, len));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]33 ut_asserteq_mem(src_buf, dst_buf, len);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]34
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]35 return 0;
36}
Simon Glass1a92f832024-08-22 07:57:48 -0600[diff] [blame]37DM_TEST(dm_test_dma_m2m, UTF_SCAN_FDT);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]38
39static int dm_test_dma(struct unit_test_state *uts)
40{
41 struct udevice *dev;
42 struct dma dma_tx, dma_rx;
43 u8 src_buf[512];
44 u8 dst_buf[512];
45 void *dst_ptr;
46 size_t len = 512;
47 u32 meta1, meta2;
48 int i;
49
50 ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
51
52 ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
53 ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
54
55 ut_assertok(dma_enable(&dma_tx));
56 ut_assertok(dma_enable(&dma_rx));
57
58 memset(dst_buf, 0, len);
59 for (i = 0; i < len; i++)
60 src_buf[i] = i;
61 meta1 = 0xADADDEAD;
62 meta2 = 0;
63 dst_ptr = &dst_buf;
64
65 ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
66
67 ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
68 ut_asserteq(0xADADDEAD, meta2);
69
70 ut_assertok(dma_disable(&dma_tx));
71 ut_assertok(dma_disable(&dma_rx));
72
73 ut_assertok(dma_free(&dma_tx));
74 ut_assertok(dma_free(&dma_rx));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]75 ut_asserteq_mem(src_buf, dst_buf, len);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]76
77 return 0;
78}
Simon Glass1a92f832024-08-22 07:57:48 -0600[diff] [blame]79DM_TEST(dm_test_dma, UTF_SCAN_FDT);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]80
81static int dm_test_dma_rx(struct unit_test_state *uts)
82{
83 struct udevice *dev;
84 struct dma dma_tx, dma_rx;
85 u8 src_buf[512];
86 u8 dst_buf[512];
87 void *dst_ptr;
88 size_t len = 512;
89 u32 meta1, meta2;
90 int i;
91
92 ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
93
94 ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
95 ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
96
97 ut_assertok(dma_enable(&dma_tx));
98 ut_assertok(dma_enable(&dma_rx));
99
100 memset(dst_buf, 0, len);
101 for (i = 0; i < len; i++)
102 src_buf[i] = i;
103 meta1 = 0xADADDEAD;
104 meta2 = 0;
105 dst_ptr = NULL;
106
107 ut_assertok(dma_prepare_rcv_buf(&dma_tx, dst_buf, len));
108
109 ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
110
111 ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
112 ut_asserteq(0xADADDEAD, meta2);
113 ut_asserteq_ptr(dst_buf, dst_ptr);
114
115 ut_assertok(dma_disable(&dma_tx));
116 ut_assertok(dma_disable(&dma_rx));
117
118 ut_assertok(dma_free(&dma_tx));
119 ut_assertok(dma_free(&dma_rx));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]120 ut_asserteq_mem(src_buf, dst_buf, len);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]121
122 return 0;
123}
Simon Glass1a92f832024-08-22 07:57:48 -0600[diff] [blame]124DM_TEST(dm_test_dma_rx, UTF_SCAN_FDT);