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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Philipp Tomsich02a61b72017-07-28 17:43:19 +02002/*
3 * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
Philipp Tomsich02a61b72017-07-28 17:43:19 +02004 */
5
Simon Glass1ea97892020-05-10 11:40:00 -06006#include <bootstage.h>
Philipp Tomsich02a61b72017-07-28 17:43:19 +02007#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Philipp Tomsichaad4d572017-09-11 22:04:16 +020011#include <dm/ofnode.h>
Philipp Tomsich02a61b72017-07-28 17:43:19 +020012#include <mapmem.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080013#include <asm/arch-rockchip/timer.h>
Philipp Tomsich02a61b72017-07-28 17:43:19 +020014#include <dt-structs.h>
15#include <timer.h>
16#include <asm/io.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20#if CONFIG_IS_ENABLED(OF_PLATDATA)
21struct rockchip_timer_plat {
Johan Jonkerf6952022023-03-07 16:30:58 +010022 struct dtd_rockchip_rk3288_timer dtd;
Philipp Tomsich02a61b72017-07-28 17:43:19 +020023};
24#endif
25
26/* Driver private data. Contains timer id. Could be either 0 or 1. */
27struct rockchip_timer_priv {
28 struct rk_timer *timer;
29};
30
Philipp Tomsichaad4d572017-09-11 22:04:16 +020031static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
Philipp Tomsich02a61b72017-07-28 17:43:19 +020032{
Philipp Tomsich02a61b72017-07-28 17:43:19 +020033 uint64_t timebase_h, timebase_l;
34 uint64_t cntr;
35
Philipp Tomsichaad4d572017-09-11 22:04:16 +020036 timebase_l = readl(&timer->timer_curr_value0);
37 timebase_h = readl(&timer->timer_curr_value1);
Philipp Tomsich02a61b72017-07-28 17:43:19 +020038
Philipp Tomsich02a61b72017-07-28 17:43:19 +020039 cntr = timebase_h << 32 | timebase_l;
Philipp Tomsichaad4d572017-09-11 22:04:16 +020040 return cntr;
41}
42
43#if CONFIG_IS_ENABLED(BOOTSTAGE)
44ulong timer_get_boot_us(void)
45{
46 uint64_t ticks = 0;
47 uint32_t rate;
48 uint64_t us;
49 int ret;
50
51 ret = dm_timer_init();
52
53 if (!ret) {
54 /* The timer is available */
55 rate = timer_get_rate(gd->timer);
56 timer_get_count(gd->timer, &ticks);
Simon Glass6d70ba02021-08-07 07:24:06 -060057 } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
Philipp Tomsichaad4d572017-09-11 22:04:16 +020058 /* We have been called so early that the DM is not ready,... */
59 ofnode node = offset_to_ofnode(-1);
60 struct rk_timer *timer = NULL;
61
62 /*
63 * ... so we try to access the raw timer, if it is specified
64 * via the tick-timer property in /chosen.
65 */
66 node = ofnode_get_chosen_node("tick-timer");
67 if (!ofnode_valid(node)) {
68 debug("%s: no /chosen/tick-timer\n", __func__);
69 return 0;
70 }
71
72 timer = (struct rk_timer *)ofnode_get_addr(node);
73
74 /* This timer is down-counting */
75 ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
76 if (ofnode_read_u32(node, "clock-frequency", &rate)) {
77 debug("%s: could not read clock-frequency\n", __func__);
78 return 0;
79 }
Philipp Tomsichaad4d572017-09-11 22:04:16 +020080 } else {
81 return 0;
82 }
83
84 us = (ticks * 1000) / rate;
85 return us;
86}
87#endif
88
Sean Anderson947fc2d2020-10-07 14:37:44 -040089static u64 rockchip_timer_get_count(struct udevice *dev)
Philipp Tomsichaad4d572017-09-11 22:04:16 +020090{
91 struct rockchip_timer_priv *priv = dev_get_priv(dev);
92 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
93
94 /* timers are down-counting */
Sean Anderson947fc2d2020-10-07 14:37:44 -040095 return ~0ull - cntr;
Philipp Tomsich02a61b72017-07-28 17:43:19 +020096}
97
Simon Glassaad29ae2020-12-03 16:55:21 -070098static int rockchip_clk_of_to_plat(struct udevice *dev)
Philipp Tomsich02a61b72017-07-28 17:43:19 +020099{
Simon Glass6d70ba02021-08-07 07:24:06 -0600100 if (CONFIG_IS_ENABLED(OF_REAL)) {
101 struct rockchip_timer_priv *priv = dev_get_priv(dev);
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200102
Simon Glass6d70ba02021-08-07 07:24:06 -0600103 priv->timer = dev_read_addr_ptr(dev);
104 if (!priv->timer)
105 return -ENOENT;
106 }
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200107
108 return 0;
109}
110
111static int rockchip_timer_start(struct udevice *dev)
112{
113 struct rockchip_timer_priv *priv = dev_get_priv(dev);
114 const uint64_t reload_val = ~0uLL;
115 const uint32_t reload_val_l = reload_val & 0xffffffff;
116 const uint32_t reload_val_h = reload_val >> 32;
117
Philipp Tomsichaad4d572017-09-11 22:04:16 +0200118 /* don't reinit, if the timer is already running and set up */
119 if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
120 (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
121 (readl(&priv->timer->timer_load_count1) == reload_val_h))
122 return 0;
123
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200124 /* disable timer and reset all control */
125 writel(0, &priv->timer->timer_ctrl_reg);
126 /* write reload value */
127 writel(reload_val_l, &priv->timer->timer_load_count0);
128 writel(reload_val_h, &priv->timer->timer_load_count1);
129 /* enable timer */
130 writel(1, &priv->timer->timer_ctrl_reg);
131
132 return 0;
133}
134
135static int rockchip_timer_probe(struct udevice *dev)
136{
137#if CONFIG_IS_ENABLED(OF_PLATDATA)
138 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
139 struct rockchip_timer_priv *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700140 struct rockchip_timer_plat *plat = dev_get_plat(dev);
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200141
Philipp Tomsich2924a362017-08-14 19:05:31 +0200142 priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200143 uc_priv->clock_rate = plat->dtd.clock_frequency;
144#endif
145
146 return rockchip_timer_start(dev);
147}
148
149static const struct timer_ops rockchip_timer_ops = {
150 .get_count = rockchip_timer_get_count,
151};
152
153static const struct udevice_id rockchip_timer_ids[] = {
Philipp Tomsich84e01142018-04-25 14:07:06 +0200154 { .compatible = "rockchip,rk3288-timer" },
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200155 {}
156};
157
Johan Jonkerf6952022023-03-07 16:30:58 +0100158U_BOOT_DRIVER(rockchip_rk3288_timer) = {
159 .name = "rockchip_rk3288_timer",
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200160 .id = UCLASS_TIMER,
161 .of_match = rockchip_timer_ids,
162 .probe = rockchip_timer_probe,
163 .ops = &rockchip_timer_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700164 .priv_auto = sizeof(struct rockchip_timer_priv),
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200165#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass71fa5b42020-12-03 16:55:18 -0700166 .plat_auto = sizeof(struct rockchip_timer_plat),
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200167#endif
Simon Glassaad29ae2020-12-03 16:55:21 -0700168 .of_to_plat = rockchip_clk_of_to_plat,
Philipp Tomsich02a61b72017-07-28 17:43:19 +0200169};