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Lukasz Majewski8c0709b2019-06-24 15:50:50 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2019
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
7#ifndef __SANDBOX_CLK_H__
8#define __SANDBOX_CLK_H__
9
10#include <linux/clk-provider.h>
11
12enum {
13 SANDBOX_CLK_PLL2 = 1,
14 SANDBOX_CLK_PLL3,
15 SANDBOX_CLK_PLL3_60M,
16 SANDBOX_CLK_PLL3_80M,
17 SANDBOX_CLK_ECSPI_ROOT,
18 SANDBOX_CLK_ECSPI0,
19 SANDBOX_CLK_ECSPI1,
20 SANDBOX_CLK_USDHC1_SEL,
21 SANDBOX_CLK_USDHC2_SEL,
Peng Fan479984c2019-07-31 07:02:02 +000022 SANDBOX_CLK_I2C,
Peng Fan8eec5102019-08-21 13:35:19 +000023 SANDBOX_CLK_I2C_ROOT,
Lukasz Majewski8c0709b2019-06-24 15:50:50 +020024};
25
26enum sandbox_pllv3_type {
27 SANDBOX_PLLV3_GENERIC,
28 SANDBOX_PLLV3_USB,
29};
30
31struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
32 const char *parent_name, void __iomem *base,
33 u32 div_mask);
34
35static inline struct clk *sandbox_clk_fixed_factor(const char *name,
36 const char *parent,
37 unsigned int mult,
38 unsigned int div)
39{
40 return clk_register_fixed_factor(NULL, name, parent,
41 CLK_SET_RATE_PARENT, mult, div);
42}
43
44static inline struct clk *sandbox_clk_divider(const char *name,
45 const char *parent,
46 void __iomem *reg, u8 shift,
47 u8 width)
48{
49 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
50 reg, shift, width, 0);
51}
52
53struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
54 const char *parent_name,
55 unsigned long flags,
56 void __iomem *reg, u8 bit_idx,
57 u8 cgr_val, u8 clk_gate_flags);
58
59static inline struct clk *sandbox_clk_gate2(const char *name,
60 const char *parent,
61 void __iomem *reg, u8 shift)
62{
63 return sandbox_clk_register_gate2(NULL, name, parent,
64 CLK_SET_RATE_PARENT, reg, shift,
65 0x3, 0);
66}
67
68static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg,
69 u8 shift, u8 width,
70 const char * const *parents,
71 int num_parents)
72{
73 return clk_register_mux(NULL, name, parents, num_parents,
74 CLK_SET_RATE_NO_REPARENT, reg, shift,
75 width, 0);
76}
77
Peng Fan8eec5102019-08-21 13:35:19 +000078int sandbox_clk_enable_count(struct clk *clk);
79
Lukasz Majewski8c0709b2019-06-24 15:50:50 +020080#endif /* __SANDBOX_CLK_H__ */