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Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
4 */
5
6#ifndef __CONFIG_PG_WCOM_LS102XA_H
7#define __CONFIG_PG_WCOM_LS102XA_H
8
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +00009/* include common defines/options for all Keymile boards */
10#include "keymile-common.h"
11
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000012#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
13#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
14
Aleksandar Gerasimovski68a89982021-06-08 14:19:08 +000015#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
16 CONFIG_KM_PHRAM + \
17 CONFIG_KM_RESERVED_PRAM) >> 10)
18
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000019#define PHYS_SDRAM 0x80000000
20#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
21
22#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
23#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
24
25#define CONFIG_DIMM_SLOTS_PER_CTLR 1
26#define CONFIG_CHIP_SELECTS_PER_CTRL 4
27
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000028#define CONFIG_SYS_SPD_BUS_NUM 0
29#define SPD_EEPROM_ADDRESS 0x54
30
Aleksandar Gerasimovskibece73e2021-06-08 14:17:34 +000031/* POST memory regions test */
32#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
33#define CONFIG_POST_EXTERNAL_WORD_FUNCS
34
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000035/*
36 * IFC Definitions
37 */
38/* NOR Flash Definitions */
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000039#define CONFIG_SYS_FLASH_BASE 0x60000000
40#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
41
42#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
43#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
44 CSPR_PORT_SIZE_16 | \
45 CSPR_TE | \
46 CSPR_MSEL_NOR | \
47 CSPR_V)
48#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
49
50#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
51 CSOR_NOR_ADM_SHIFT(0x4) | \
52 CSOR_NOR_NOR_MODE_ASYNC_NOR | \
53 CSOR_NOR_TRHZ_20 | \
54 CSOR_NOR_BCTLD)
55#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
56 FTIM0_NOR_TEADC(0x7) | \
57 FTIM0_NOR_TAVDS(0x0) | \
58 FTIM0_NOR_TEAHC(0x1))
59#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
60 FTIM1_NOR_TRAD_NOR(0x21) | \
61 FTIM1_NOR_TSEQRAD_NOR(0x21))
62#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
63 FTIM2_NOR_TCH(0x1) | \
64 FTIM2_NOR_TWPH(0x6) | \
65 FTIM2_NOR_TWP(0xb))
66#define CONFIG_SYS_NOR_FTIM3 0
67
68#define CONFIG_SYS_FLASH_QUIET_TEST
69#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
70
71#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
72#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
73#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
74#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
75
76#define CONFIG_SYS_FLASH_EMPTY_INFO
77#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
78
79#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
80#define CONFIG_SYS_WRITE_SWAPPED_DATA
81
82#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
83#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
84#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
85#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
86#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
87#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
88#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
89#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
90
91/* NAND Flash Definitions */
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000092#define CONFIG_SYS_NAND_BASE 0x68000000
93#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
94
95#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
96#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
97 CSPR_PORT_SIZE_8 | \
98 CSPR_TE | \
99 CSPR_MSEL_NAND | \
100 CSPR_V)
101#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
102#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
103 | CSOR_NAND_ECC_DEC_EN \
104 | CSOR_NAND_ECC_MODE_4 \
105 | CSOR_NAND_RAL_3 \
106 | CSOR_NAND_PGS_2K \
107 | CSOR_NAND_SPRZ_64 \
108 | CSOR_NAND_PB(64) \
109 | CSOR_NAND_TRHZ_40 \
110 | CSOR_NAND_BCTLD)
111
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000112#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
113 FTIM0_NAND_TWP(0x8) | \
114 FTIM0_NAND_TWCHT(0x3) | \
115 FTIM0_NAND_TWH(0x5))
116#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
117 FTIM1_NAND_TWBE(0x1e) | \
118 FTIM1_NAND_TRR(0x6) | \
119 FTIM1_NAND_TRP(0x8))
120#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
121 FTIM2_NAND_TREH(0x5) | \
122 FTIM2_NAND_TWHRE(0x3c))
123#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
124
125#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
126#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
127#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
128#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
129#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
130#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
131#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
132#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
133
134#define CONFIG_SYS_MAX_NAND_DEVICE 1
135#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000136
137/* QRIO FPGA Definitions */
138#define CONFIG_SYS_QRIO_BASE 0x70000000
139#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
140
141#define CONFIG_SYS_CSPR2_EXT (0x00)
142#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
143 CSPR_PORT_SIZE_8 | \
144 CSPR_TE | \
145 CSPR_MSEL_GPCM | \
146 CSPR_V)
147#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
148#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
149 CSOR_GPCM_TRHZ_20 | \
150 CSOR_GPCM_BCTLD)
151#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
152 FTIM0_GPCM_TEADC(0x8) | \
153 FTIM0_GPCM_TEAHC(0x2))
154#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
155 FTIM1_GPCM_TRAD(0x6))
156#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
157 FTIM2_GPCM_TCH(0x1) | \
158 FTIM2_GPCM_TWP(0x7))
159#define CONFIG_SYS_CS2_FTIM3 0x04000000
160
161/*
162 * Serial Port
163 */
164#define CONFIG_SYS_NS16550_SERIAL
165#define CONFIG_SYS_NS16550_CLK get_serial_clock()
166
167/*
168 * I2C
169 */
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000170#define CONFIG_SYS_I2C_INIT_BOARD
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000171
172#define CONFIG_I2C_MULTI_BUS
173#define CONFIG_SYS_I2C_MAX_HOPS 1
174#define CONFIG_SYS_NUM_I2C_BUSES 3
175#define I2C_MUX_PCA_ADDR 0x70
176#define I2C_MUX_CH_DEFAULT 0x0
177#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
178 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
179 {1, {I2C_NULL_HOP} }, \
180 }
181
182/*
183 * eTSEC
184 */
185#ifdef CONFIG_TSEC_ENET
186#define CONFIG_ETHPRIME "ethernet@2d90000"
187#endif
188
189#define CONFIG_LAYERSCAPE_NS_ACCESS
190#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Aleksandar Gerasimovskiff002e62021-06-08 14:25:21 +0000191#define COUNTER_FREQUENCY 8333333
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000192
193#define CONFIG_HWCONFIG
194#define HWCONFIG_BUFFER_SIZE 256
195#define CONFIG_FSL_DEVICE_DISABLE
196
197/*
198 * Miscellaneous configurable options
199 */
200
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000201#define CONFIG_LS102XA_STREAM_ID
202
203#define CONFIG_SYS_INIT_SP_OFFSET \
204 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
205#define CONFIG_SYS_INIT_SP_ADDR \
206 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
207
208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
209#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000210
211#define CONFIG_SYS_BOOTCOUNT_BE
212
213/*
214 * Environment
215 */
216
217#define CONFIG_ENV_TOTAL_SIZE 0x40000
218#define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */
219
220#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
221#define CONFIG_KM_DEF_ENV
222#endif
223
224#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
225#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
226#endif
227
228#define CONFIG_KM_DEF_ENV_CPU \
229 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
230 "cramfsloadfdt=" \
231 "cramfsload ${fdt_addr_r} " \
232 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
233 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
234 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
235 " +${filesize} && " \
236 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
237 " +${filesize} && " \
238 "cp.b ${load_addr_r} " \
239 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
240 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
241 " +${filesize}\0" \
242 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
243 " +${filesize} && " \
244 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
245 " +${filesize} && " \
246 "cp.b ${load_addr_r} " \
247 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
248 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
249 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
250 "set_fdthigh=true\0" \
251 "checkfdt=true\0" \
252 ""
253
254#define CONFIG_KM_NEW_ENV \
255 "newenv=protect off " __stringify(ENV_DEL_ADDR) \
256 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
257 "erase " __stringify(ENV_DEL_ADDR) \
258 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
259 "protect on " __stringify(ENV_DEL_ADDR) \
260 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
261
Aleksandar Gerasimovski56c6c2c2021-06-08 14:23:34 +0000262#define CONFIG_HW_ENV_SETTINGS \
263 "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \
264 "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \
265 "asrc,spdif,lpuart1,ftm1\0"
266
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000267#define CONFIG_EXTRA_ENV_SETTINGS \
268 CONFIG_KM_NEW_ENV \
269 CONFIG_KM_DEF_ENV \
Aleksandar Gerasimovski56c6c2c2021-06-08 14:23:34 +0000270 CONFIG_HW_ENV_SETTINGS \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000271 "EEprom_ivm=pca9547:70:9\0" \
Aleksandar Gerasimovskia5ac0a42021-06-08 14:21:15 +0000272 "ethrotate=no\0" \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000273 ""
274
275#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
276#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
277
278#endif