Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Atmel Corporation |
| 4 | * Wenyou.Yang <wenyou.yang@atmel.com> |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __AT91_PMC_H__ |
| 8 | #define __AT91_PMC_H__ |
| 9 | |
Claudiu Beznea | 8fdb425 | 2020-09-07 17:46:38 +0300 | [diff] [blame] | 10 | #include <linux/bitops.h> |
| 11 | #include <linux/io.h> |
| 12 | |
| 13 | /* Keep a range of 256 available clocks for every clock type. */ |
| 14 | #define AT91_TO_CLK_ID(_t, _i) (((_t) << 8) | ((_i) & 0xff)) |
| 15 | #define AT91_CLK_ID_TO_DID(_i) ((_i) & 0xff) |
Wenyou Yang | 6b66b92 | 2017-09-05 18:30:07 +0800 | [diff] [blame] | 16 | |
Claudiu Beznea | 923ac87 | 2020-09-07 17:46:42 +0300 | [diff] [blame] | 17 | struct clk_range { |
| 18 | unsigned long min; |
| 19 | unsigned long max; |
| 20 | }; |
| 21 | |
Claudiu Beznea | 1f9023a | 2020-09-07 17:46:43 +0300 | [diff] [blame] | 22 | struct clk_master_layout { |
| 23 | u32 offset; |
| 24 | u32 mask; |
| 25 | u8 pres_shift; |
| 26 | }; |
| 27 | |
| 28 | extern const struct clk_master_layout at91rm9200_master_layout; |
| 29 | extern const struct clk_master_layout at91sam9x5_master_layout; |
| 30 | |
| 31 | struct clk_master_characteristics { |
| 32 | struct clk_range output; |
Eugen Hristev | 227fa12 | 2020-07-01 10:42:58 +0300 | [diff] [blame] | 33 | u32 divisors[5]; |
Claudiu Beznea | 1f9023a | 2020-09-07 17:46:43 +0300 | [diff] [blame] | 34 | u8 have_div3_pres; |
| 35 | }; |
| 36 | |
Claudiu Beznea | 923ac87 | 2020-09-07 17:46:42 +0300 | [diff] [blame] | 37 | struct clk_pll_characteristics { |
| 38 | struct clk_range input; |
| 39 | int num_output; |
| 40 | const struct clk_range *output; |
| 41 | u16 *icpll; |
| 42 | u8 *out; |
| 43 | u8 upll : 1; |
| 44 | }; |
| 45 | |
| 46 | struct clk_pll_layout { |
| 47 | u32 pllr_mask; |
| 48 | u32 mul_mask; |
| 49 | u32 frac_mask; |
| 50 | u32 div_mask; |
| 51 | u32 endiv_mask; |
| 52 | u8 mul_shift; |
| 53 | u8 frac_shift; |
| 54 | u8 div_shift; |
| 55 | u8 endiv_shift; |
| 56 | }; |
| 57 | |
Claudiu Beznea | d96487b | 2020-09-07 17:46:47 +0300 | [diff] [blame] | 58 | struct clk_programmable_layout { |
| 59 | u8 pres_mask; |
| 60 | u8 pres_shift; |
| 61 | u8 css_mask; |
| 62 | u8 have_slck_mck; |
| 63 | u8 is_pres_direct; |
| 64 | }; |
| 65 | |
Claudiu Beznea | d0c738b | 2020-09-07 17:46:49 +0300 | [diff] [blame] | 66 | struct clk_pcr_layout { |
| 67 | u32 offset; |
| 68 | u32 cmd; |
| 69 | u32 div_mask; |
| 70 | u32 gckcss_mask; |
| 71 | u32 pid_mask; |
| 72 | }; |
| 73 | |
Claudiu Beznea | d96487b | 2020-09-07 17:46:47 +0300 | [diff] [blame] | 74 | extern const struct clk_programmable_layout at91rm9200_programmable_layout; |
| 75 | extern const struct clk_programmable_layout at91sam9g45_programmable_layout; |
| 76 | extern const struct clk_programmable_layout at91sam9x5_programmable_layout; |
| 77 | |
Claudiu Beznea | 6fa9898 | 2020-09-07 17:46:51 +0300 | [diff] [blame] | 78 | extern const struct clk_ops at91_clk_ops; |
| 79 | |
Claudiu Beznea | 5d40887 | 2020-09-07 17:46:41 +0300 | [diff] [blame] | 80 | struct clk *at91_clk_main_rc(void __iomem *reg, const char *name, |
| 81 | const char *parent_name); |
| 82 | struct clk *at91_clk_main_osc(void __iomem *reg, const char *name, |
| 83 | const char *parent_name, bool bypass); |
| 84 | struct clk *at91_clk_rm9200_main(void __iomem *reg, const char *name, |
| 85 | const char *parent_name); |
| 86 | struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name, |
| 87 | const char * const *parent_names, int num_parents, |
| 88 | const u32 *mux_table, int type); |
Claudiu Beznea | 923ac87 | 2020-09-07 17:46:42 +0300 | [diff] [blame] | 89 | struct clk * |
| 90 | sam9x60_clk_register_div_pll(void __iomem *base, const char *name, |
| 91 | const char *parent_name, u8 id, |
| 92 | const struct clk_pll_characteristics *characteristics, |
| 93 | const struct clk_pll_layout *layout, bool critical); |
| 94 | struct clk * |
| 95 | sam9x60_clk_register_frac_pll(void __iomem *base, const char *name, |
| 96 | const char *parent_name, u8 id, |
| 97 | const struct clk_pll_characteristics *characteristics, |
| 98 | const struct clk_pll_layout *layout, bool critical); |
Claudiu Beznea | 1f9023a | 2020-09-07 17:46:43 +0300 | [diff] [blame] | 99 | struct clk * |
Claudiu Beznea | 8b5bbad | 2021-07-16 08:43:48 +0300 | [diff] [blame] | 100 | at91_clk_register_master_pres(void __iomem *base, const char *name, |
Claudiu Beznea | 1f9023a | 2020-09-07 17:46:43 +0300 | [diff] [blame] | 101 | const char * const *parent_names, int num_parents, |
| 102 | const struct clk_master_layout *layout, |
| 103 | const struct clk_master_characteristics *characteristics, |
| 104 | const u32 *mux_table); |
Claudiu Beznea | e812b02 | 2020-09-07 17:46:44 +0300 | [diff] [blame] | 105 | struct clk * |
Claudiu Beznea | 8b5bbad | 2021-07-16 08:43:48 +0300 | [diff] [blame] | 106 | at91_clk_register_master_div(void __iomem *base, |
| 107 | const char *name, const char *parent_name, |
| 108 | const struct clk_master_layout *layout, |
| 109 | const struct clk_master_characteristics *characteristics); |
| 110 | struct clk * |
Claudiu Beznea | e812b02 | 2020-09-07 17:46:44 +0300 | [diff] [blame] | 111 | at91_clk_sama7g5_register_master(void __iomem *base, const char *name, |
| 112 | const char * const *parent_names, int num_parents, |
| 113 | const u32 *mux_table, const u32 *clk_mux_table, |
| 114 | bool critical, u8 id); |
Claudiu Beznea | 96179bd | 2020-09-07 17:46:45 +0300 | [diff] [blame] | 115 | struct clk * |
| 116 | at91_clk_register_utmi(void __iomem *base, struct udevice *dev, |
| 117 | const char *name, const char *parent_name); |
Claudiu Beznea | 6b5fa94 | 2020-09-07 17:46:46 +0300 | [diff] [blame] | 118 | struct clk * |
| 119 | at91_clk_sama7g5_register_utmi(void __iomem *base, const char *name, |
| 120 | const char *parent_name); |
Claudiu Beznea | d96487b | 2020-09-07 17:46:47 +0300 | [diff] [blame] | 121 | struct clk * |
| 122 | at91_clk_register_programmable(void __iomem *base, const char *name, |
| 123 | const char * const *parent_names, u8 num_parents, u8 id, |
| 124 | const struct clk_programmable_layout *layout, |
| 125 | const u32 *clk_mux_table, const u32 *mux_table); |
Claudiu Beznea | ccb83c6 | 2020-09-07 17:46:48 +0300 | [diff] [blame] | 126 | struct clk * |
| 127 | at91_clk_register_system(void __iomem *base, const char *name, |
| 128 | const char *parent_name, u8 id); |
Claudiu Beznea | d0c738b | 2020-09-07 17:46:49 +0300 | [diff] [blame] | 129 | struct clk * |
| 130 | at91_clk_register_peripheral(void __iomem *base, const char *name, |
| 131 | const char *parent_name, u32 id); |
| 132 | struct clk * |
| 133 | at91_clk_register_sam9x5_peripheral(void __iomem *base, |
| 134 | const struct clk_pcr_layout *layout, |
| 135 | const char *name, const char *parent_name, |
| 136 | u32 id, const struct clk_range *range); |
Claudiu Beznea | 00e9b9a | 2020-09-07 17:46:50 +0300 | [diff] [blame] | 137 | struct clk * |
| 138 | at91_clk_register_generic(void __iomem *base, |
| 139 | const struct clk_pcr_layout *layout, const char *name, |
| 140 | const char * const *parent_names, |
| 141 | const u32 *clk_mux_table, const u32 *mux_table, |
| 142 | u8 num_parents, u8 id, const struct clk_range *range); |
Claudiu Beznea | 5d40887 | 2020-09-07 17:46:41 +0300 | [diff] [blame] | 143 | |
Claudiu Beznea | 8fdb425 | 2020-09-07 17:46:38 +0300 | [diff] [blame] | 144 | int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val); |
| 145 | int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index); |
| 146 | |
| 147 | void pmc_read(void __iomem *base, unsigned int off, unsigned int *val); |
| 148 | void pmc_write(void __iomem *base, unsigned int off, unsigned int val); |
| 149 | void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask, |
| 150 | unsigned int bits); |
Claudiu Beznea | 3f203a1 | 2020-09-07 17:46:39 +0300 | [diff] [blame] | 151 | |
Wenyou Yang | 8c772bd | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 152 | #endif |