maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 1 | if ARCH_ASPEED |
| 2 | |
| 3 | config SYS_ARCH |
| 4 | default "arm" |
| 5 | |
| 6 | config SYS_SOC |
| 7 | default "aspeed" |
| 8 | |
| 9 | config SYS_TEXT_BASE |
| 10 | default 0x00000000 |
| 11 | |
Chia-Wei, Wang | 8f7f490 | 2020-12-14 13:54:28 +0800 | [diff] [blame] | 12 | choice |
| 13 | prompt "Aspeed SoC select" |
| 14 | depends on ARCH_ASPEED |
| 15 | default ASPEED_AST2500 |
| 16 | |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 17 | config ASPEED_AST2500 |
| 18 | bool "Support Aspeed AST2500 SoC" |
maxims@google.com | 0fdb11a | 2017-04-17 12:00:26 -0700 | [diff] [blame] | 19 | depends on DM_RESET |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 20 | select CPU_ARM1176 |
| 21 | help |
| 22 | The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. |
| 23 | It is used as Board Management Controller on many server boards, |
| 24 | which is enabled by support of LPC and eSPI peripherals. |
| 25 | |
Chia-Wei, Wang | 8f7f490 | 2020-12-14 13:54:28 +0800 | [diff] [blame] | 26 | config ASPEED_AST2600 |
| 27 | bool "Support Aspeed AST2600 SoC" |
| 28 | select CPU_V7A |
| 29 | select CPU_V7_HAS_NONSEC |
| 30 | select SYS_ARCH_TIMER |
| 31 | select SUPPORT_SPL |
| 32 | select ENABLE_ARM_SOC_BOOT0_HOOK |
| 33 | help |
| 34 | The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU. |
| 35 | It is used as Board Management Controller on many server boards, |
| 36 | which is enabled by support of LPC and eSPI peripherals. |
| 37 | |
| 38 | endchoice |
| 39 | |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 40 | source "arch/arm/mach-aspeed/ast2500/Kconfig" |
Chia-Wei, Wang | 8f7f490 | 2020-12-14 13:54:28 +0800 | [diff] [blame] | 41 | source "arch/arm/mach-aspeed/ast2600/Kconfig" |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 42 | |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 43 | endif |