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TsiChungLiew8cb946d2008-01-15 14:15:46 -06001/*
2 * Configuation settings for the Freescale MCF5485 FireEngine board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew8cb946d2008-01-15 14:15:46 -06008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5485EVB_H
15#define _M5485EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChungLiew8cb946d2008-01-15 14:15:46 -060021
Alison Wang8f6d8f32015-02-12 18:33:15 +080022#define CONFIG_DISPLAY_BOARDINFO
23
TsiChungLiew8cb946d2008-01-15 14:15:46 -060024#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew8cb946d2008-01-15 14:15:46 -060026#define CONFIG_BAUDRATE 115200
TsiChungLiew8cb946d2008-01-15 14:15:46 -060027
Alison Wang8f6d8f32015-02-12 18:33:15 +080028#undef CONFIG_HW_WATCHDOG
TsiChungLiew8cb946d2008-01-15 14:15:46 -060029#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
30
31/* Command line configuration */
TsiChungLiew8cb946d2008-01-15 14:15:46 -060032#undef CONFIG_CMD_DATE
TsiChungLiew8cb946d2008-01-15 14:15:46 -060033#define CONFIG_CMD_PCI
TsiChungLiew8cb946d2008-01-15 14:15:46 -060034#define CONFIG_CMD_REGINFO
TsiChungLiew8cb946d2008-01-15 14:15:46 -060035
36#define CONFIG_SLTTMR
37
38#define CONFIG_FSLDMAFEC
39#ifdef CONFIG_FSLDMAFEC
TsiChungLiew8cb946d2008-01-15 14:15:46 -060040# define CONFIG_MII 1
TsiChung Liewb3162452008-03-30 01:22:13 -050041# define CONFIG_MII_INIT 1
TsiChungLiew8cb946d2008-01-15 14:15:46 -060042# define CONFIG_HAS_ETH1
43
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044# define CONFIG_SYS_DMA_USE_INTSRAM 1
45# define CONFIG_SYS_DISCOVER_PHY
46# define CONFIG_SYS_RX_ETH_BUFFER 32
47# define CONFIG_SYS_TX_ETH_BUFFER 48
48# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8cb946d2008-01-15 14:15:46 -060049
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050# define CONFIG_SYS_FEC0_PINMUX 0
51# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
52# define CONFIG_SYS_FEC1_PINMUX 0
53# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChungLiew8cb946d2008-01-15 14:15:46 -060054
Wolfgang Denka1be4762008-05-20 16:00:29 +020055# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
57# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew8cb946d2008-01-15 14:15:46 -060058# define FECDUPLEX FULL
59# define FECSPEED _100BASET
60# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
62# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8cb946d2008-01-15 14:15:46 -060063# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew8cb946d2008-01-15 14:15:46 -060065
TsiChungLiew8cb946d2008-01-15 14:15:46 -060066# define CONFIG_IPADDR 192.162.1.2
67# define CONFIG_NETMASK 255.255.255.0
68# define CONFIG_SERVERIP 192.162.1.1
69# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiew8cb946d2008-01-15 14:15:46 -060070
71#endif
72
73#ifdef CONFIG_CMD_USB
TsiChungLiew8cb946d2008-01-15 14:15:46 -060074# define CONFIG_DOS_PARTITION
75# define CONFIG_USB_OHCI_NEW
76# ifndef CONFIG_CMD_PCI
77# define CONFIG_CMD_PCI
78# endif
79/*# define CONFIG_PCI_OHCI*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
81# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
82# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
83# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
TsiChungLiew8cb946d2008-01-15 14:15:46 -060084#endif
85
86/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +020087#define CONFIG_SYS_I2C
88#define CONFIG_SYS_I2C_FSL
89#define CONFIG_SYS_FSL_I2C_SPEED 80000
90#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
91#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew8cb946d2008-01-15 14:15:46 -060093
94/* PCI */
95#ifdef CONFIG_CMD_PCI
96#define CONFIG_PCI 1
97#define CONFIG_PCI_PNP 1
TsiChung Liew521f97b2008-03-30 01:19:06 -050098#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew8cb946d2008-01-15 14:15:46 -060099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
101#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
102#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600103
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_PCI_IO_BUS 0x71000000
105#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
106#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
109#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
110#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600111#endif
112
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600113#define CONFIG_UDP_CHECKSUM
114
115#define CONFIG_HOSTNAME M548xEVB
116#define CONFIG_EXTRA_ENV_SETTINGS \
117 "netdev=eth0\0" \
118 "loadaddr=10000\0" \
119 "u-boot=u-boot.bin\0" \
120 "load=tftp ${loadaddr) ${u-boot}\0" \
121 "upd=run load; run prog\0" \
122 "prog=prot off bank 1;" \
Jason Jinded4eb42011-08-19 10:10:40 +0800123 "era ff800000 ff83ffff;" \
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600124 "cp.b ${loadaddr} ff800000 ${filesize};"\
125 "save\0" \
126 ""
127
128#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600130
131#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600133#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600135#endif
136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
138#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
140#define CONFIG_SYS_LOAD_ADDR 0x00010000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
143#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_MBAR 0xF0000000
146#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
147#define CONFIG_SYS_INTSRAMSZ 0x8000
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600148
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600150
151/*
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
155 */
156/*-----------------------------------------------------------------------
157 * Definitions for initial stack pointer and data area (in DPRAM)
158 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200160#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161#define CONFIG_SYS_INIT_RAM_CTRL 0x21
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200162#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
164#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
Wolfgang Denk0191e472010-10-26 14:34:52 +0200165#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600172 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_SDRAM_BASE 0x00000000
174#define CONFIG_SYS_SDRAM_CFG1 0x73711630
175#define CONFIG_SYS_SDRAM_CFG2 0x46770000
176#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
177#define CONFIG_SYS_SDRAM_EMOD 0x40010000
178#define CONFIG_SYS_SDRAM_MODE 0x018D0000
179#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
180#ifdef CONFIG_SYS_DRAMSZ1
181# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600182#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600184#endif
185
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
187#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600188
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
190#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600191
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600193
Jason Jinded4eb42011-08-19 10:10:40 +0800194/* Reserve 256 kB for malloc() */
195#define CONFIG_SYS_MALLOC_LEN (256 << 10)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization ??
200 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600202
203/*-----------------------------------------------------------------------
204 * FLASH organization
205 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_CFI
207#ifdef CONFIG_SYS_FLASH_CFI
208# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200209# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
211# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
212# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
213# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
214#ifdef CONFIG_SYS_NOR1SZ
215# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
216# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
217# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600218#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
220# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600221#endif
222#endif
223
224/* Configuration for environment
Jason Jinded4eb42011-08-19 10:10:40 +0800225 * Environment is not embedded in u-boot. First time runing may have env
226 * crc error warning if there is no correct environment on the flash.
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600227 */
Jason Jinded4eb42011-08-19 10:10:40 +0800228#define CONFIG_ENV_OFFSET 0x40000
229#define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200230#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600231
232/*-----------------------------------------------------------------------
233 * Cache Configuration
234 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600236
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600237#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200238 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600239#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200240 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600241#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
242 CF_CACR_IDCM)
243#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
244#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
245 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
246 CF_ACR_EN | CF_ACR_SM_ALL)
247#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
248 CF_CACR_IEC | CF_CACR_ICINVA)
249#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
250 CF_CACR_DEC | CF_CACR_DDCM_P | \
251 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
252
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600253/*-----------------------------------------------------------------------
254 * Chipselect bank definitions
255 */
256/*
257 * CS0 - NOR Flash 1, 2, 4, or 8MB
258 * CS1 - NOR Flash
259 * CS2 - Available
260 * CS3 - Available
261 * CS4 - Available
262 * CS5 - Available
263 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_CS0_BASE 0xFF800000
265#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
266#define CONFIG_SYS_CS0_CTRL 0x00101980
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600267
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#ifdef CONFIG_SYS_NOR1SZ
269#define CONFIG_SYS_CS1_BASE 0xE0000000
270#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
271#define CONFIG_SYS_CS1_CTRL 0x00101D80
TsiChungLiew8cb946d2008-01-15 14:15:46 -0600272#endif
273
274#endif /* _M5485EVB_H */