Blame - board/gdsys/405ex/405ex.c - filogic/uboot

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#include <common.h>

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#include <asm/ppc4xx.h>

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#include <asm/ppc405.h>

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#include <asm/processor.h>

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#include <asm/io.h>

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#include <gdsys_fpga.h>

#include "405ex.h"

#define REFLECTION_TESTPATTERN 0xdede

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#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)

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#ifdef CONFIG_SYS_FPGA_NO_RFL_HI

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#define REFLECTION_TESTREG reflection_low

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#else

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#define REFLECTION_TESTREG reflection_high

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#endif

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DECLARE_GLOBAL_DATA_PTR;

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int get_fpga_state(unsigned dev)

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{

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return gd->arch.fpga_state[dev];

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}

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void print_fpga_state(unsigned dev)

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{

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if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)

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puts(" Waiting for FPGA-DONE timed out.\n");

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if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)

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puts(" FPGA reflection test failed.\n");

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}

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int board_early_init_f(void)

{

u32 val;

/*--------------------------------------------------------------------+

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| Interrupt controller setup

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+--------------------------------------------------------------------+

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+---------------------------------------------------------------------+

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+---------+-----------------------------------+-------+-------+-------+

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| IRQ 02 | IIC0 | High | Level | Non |

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| IRQ 03 | TBD | High | Level | Non |

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| IRQ 04 | TBD | High | Level | Non |

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| IRQ 05 | EBM | High | Level | Non |

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| IRQ 06 | BGI | High | Level | Non |

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| IRQ 07 | IIC1 | Rising| Edge | Non |

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| IRQ 08 | SPI | High | Lvl/ed| Non |

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| IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |

| IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |

|----------------------------------------------------------------------

| IRQ 37 | EBC | High |Lvl Edg| Non |

|----------------------------------------------------------------------

| IRQ 71 | Reserved | N/A | N/A | Non |

| IRQ 79 | Reserved | N/A | N/A | Non |

| IRQ 87 | Reserved | N/A | N/A | Non |

| IRQ 94 | Reserved | N/A | N/A | Non |

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| IRQ 95 | Reserved | N/A | N/A | Non |

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|---------------------------------------------------------------------

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+---------+-----------------------------------+-------+-------+------*/

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/*--------------------------------------------------------------------+

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| Initialise UIC registers. Clear all interrupts. Disable all

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| interrupts.

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| Set critical interrupt values. Set interrupt polarities. Set

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| interrupt trigger levels. Make bit 0 High priority. Clear all

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| interrupts again.

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+-------------------------------------------------------------------*/

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mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */

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mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */

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mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */

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mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */

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mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */

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mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */

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mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */

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mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */

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mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */

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mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */

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mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */

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mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */

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mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */

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mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */

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mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */

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mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */

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mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */

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mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */

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/* Except cascade UIC0 and UIC1 */

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mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */

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mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */

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mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */

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mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */

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mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */

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mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */

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/*

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* Note: Some cores are still in reset when the chip starts, so

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* take them out of reset

*/

mtsdr(SDR0_SRST, 0);

/*

* Configure PFC (Pin Function Control) registers

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*/

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val = SDR0_PFC1_GPT_FREQ;

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mtsdr(SDR0_PFC1, val);

return 0;

}

int board_early_init_r(void)

{

unsigned k;

unsigned ctr;

for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)

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gd->arch.fpga_state[k] = 0;

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/*

* reset FPGA

*/

gd405ex_init();

gd405ex_set_fpga_reset(1);

gd405ex_setup_hw();

for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {

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ctr = 0;

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while (!gd405ex_get_fpga_done(k)) {

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udelay(100000);

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if (ctr++ > 5) {

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gd->arch.fpga_state[k] |=

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FPGA_STATE_DONE_FAILED;

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break;

}

}

}

udelay(10);

gd405ex_set_fpga_reset(0);

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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {

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/*

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* wait for fpga out of reset

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*/

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ctr = 0;

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while (1) {

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u16 val;

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FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);

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FPGA_GET_REG(k, REFLECTION_TESTREG, &val);

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if (val == REFLECTION_TESTPATTERN_INV)

Dirk Eibach

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break;

udelay(100000);

if (ctr++ > 5) {

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gd->arch.fpga_state[k] |=

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FPGA_STATE_REFLECTION_FAILED;

break;

}

}

}

return 0;

}