| Stefan Kristiansson | 6e560bb | 2011-11-26 19:04:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Kristiansson | 6e560bb | 2011-11-26 19:04:49 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_OPENRISC_CACHE_H_ |
| 8 | #define __ASM_OPENRISC_CACHE_H_ |
| 9 | |
| 10 | /* |
| 11 | * Valid L1 data cache line sizes for the OpenRISC architecture are |
| 12 | * 16 and 32 bytes. |
| 13 | * If the board configuration has not specified one we default to the |
| 14 | * largest of these values for alignment of DMA buffers. |
| 15 | */ |
| 16 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 17 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 18 | #else |
| 19 | #define ARCH_DMA_MINALIGN 32 |
| 20 | #endif |
| 21 | |
| 22 | #endif /* __ASM_OPENRISC_CACHE_H_ */ |