blob: 6f1304dc9432e374b9f8203d3e3f77d72fb79d64 [file] [log] [blame]
Tom Rixc5a51352009-10-17 12:41:06 -05001/*
2 * (C) Copyright 2006-2009
3 * Texas Instruments Incorporated.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 *
8 * Configuration settings for the 3430 TI SDP3430 board.
9 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Tom Rixc5a51352009-10-17 12:41:06 -050011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/* TODO: REMOVE THE FOLLOWING
17 * Retained the following till size.h is removed in u-boot
18 */
19#include <asm/sizes.h>
20/*
21 * High Level Configuration Options
22 */
Tom Rixc5a51352009-10-17 12:41:06 -050023#define CONFIG_OMAP 1 /* in a TI OMAP core */
24#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Tom Rixc5a51352009-10-17 12:41:06 -050025#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
Lokesh Vutla56055052013-07-30 11:36:30 +053026#define CONFIG_OMAP_COMMON
Tom Rixc5a51352009-10-17 12:41:06 -050027
Vaibhav Hiremath558d23d2010-06-07 15:20:34 -040028#define CONFIG_SDRC /* The chip has SDRC controller */
29
Tom Rixc5a51352009-10-17 12:41:06 -050030#include <asm/arch/cpu.h> /* get chip and board defs */
31#include <asm/arch/omap3.h>
32
33/*
34 * NOTE: these #defines presume standard SDP jumper settings.
35 * In particular:
36 * - 26 MHz clock (not 19.2 or 38.4 MHz)
37 * - Boot from 128MB NOR, not NAND or OneNAND
38 *
39 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
40 * support for all the flash types the board supports.
41 */
42#define CONFIG_DISPLAY_CPUINFO 1
43#define CONFIG_DISPLAY_BOARDINFO 1
44
45/* Clock Defines */
46#define V_OSCK 26000000 /* Clock output from T2 */
47#define V_SCLK (V_OSCK >> 1)
48
Tom Rixc5a51352009-10-17 12:41:06 -050049#define CONFIG_MISC_INIT_R
50
51#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
52#define CONFIG_SETUP_MEMORY_TAGS 1
53#define CONFIG_INITRD_TAG 1
54#define CONFIG_REVISION_TAG 1
55
Grant Likely100b8492011-03-28 09:59:07 +000056#define CONFIG_OF_LIBFDT 1
57
Tom Rixc5a51352009-10-17 12:41:06 -050058/*
59 * Size of malloc() pool
60 * Total Size Environment - 256k
61 * Malloc - add 256k
62 */
63#define CONFIG_ENV_SIZE (256 << 10)
64#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
Tom Rixc5a51352009-10-17 12:41:06 -050065
66/*--------------------------------------------------------------------------*/
67
68/*
69 * Hardware drivers
70 */
71
72/*
73 * TWL4030
74 */
75#define CONFIG_TWL4030_POWER 1
76
77/*
78 * serial port - NS16550 compatible
79 */
80#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
81
82#define CONFIG_SYS_NS16550
83#define CONFIG_SYS_NS16550_SERIAL
84#define CONFIG_SYS_NS16550_REG_SIZE (-4)
85#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86
87/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
88 * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
89 * support UART boot (that's only for UART3); it prevents sharing a Linux
90 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
91 *
92 * UART boot uses UART3 on J9, and the SDP user's guide says to use
93 * that for console. Downsides of using J9: you can't use IRDA too;
94 * since UART3 isn't in the CORE power domain, it may be a bit less
95 * usable in certain PM-sensitive debug scenarios.
96 */
97#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
98
99#ifdef CONSOLE_J9
100#define CONFIG_CONS_INDEX 3
101#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
102#define CONFIG_SERIAL3 3 /* UART3 */
103#else
104#define CONFIG_CONS_INDEX 1
105#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
106#define CONFIG_SERIAL1 1 /* UART1 */
107#endif
108
109#define CONFIG_ENV_OVERWRITE
110#define CONFIG_BAUDRATE 115200
111#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
112 115200}
113
114/*
115 * I2C for power management setup
116 */
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200117#define CONFIG_SYS_I2C
118#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
119#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
120#define CONFIG_SYS_I2C_OMAP34XX
Tom Rixc5a51352009-10-17 12:41:06 -0500121
Tom Rixc5a51352009-10-17 12:41:06 -0500122/* OMITTED: single 1 Gbit MT29F1G NAND flash */
123
124/*
125 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
126 */
127#define CONFIG_SYS_FLASH_BASE 0x10000000
128#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
129#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
130#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
131#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
132#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
133#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
134#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
135
136#define CONFIG_SYS_FLASH_CFI_WIDTH 2
137#define PHYS_FLASH_SIZE (128 << 20)
138#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
139
Tom Rixc5a51352009-10-17 12:41:06 -0500140/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
141
142#define CONFIG_ENV_IS_IN_FLASH 1
143#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
144#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
145#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
146/*--------------------------------------------------------------------------*/
147
148/* commands to include */
149#include <config_cmd_default.h>
150
151/* Enabled commands */
152#define CONFIG_CMD_DHCP /* DHCP Support */
153#define CONFIG_CMD_EXT2 /* EXT2 Support */
154#define CONFIG_CMD_FAT /* FAT support */
155#define CONFIG_CMD_I2C /* I2C serial bus support */
156#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
157#define CONFIG_CMD_MMC /* MMC support */
158#define CONFIG_CMD_NET
159
160/* Disabled commands */
161#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
162#undef CONFIG_CMD_IMLS /* List all found images */
163
164/*--------------------------------------------------------------------------*/
165/*
166 * MMC boot support
167 */
168
169#if defined(CONFIG_CMD_MMC)
Tom Rini286dae32011-09-03 21:52:21 -0400170#define CONFIG_GENERIC_MMC 1
Tom Rixc5a51352009-10-17 12:41:06 -0500171#define CONFIG_MMC 1
Tom Rini286dae32011-09-03 21:52:21 -0400172#define CONFIG_OMAP_HSMMC 1
Tom Rixc5a51352009-10-17 12:41:06 -0500173#define CONFIG_DOS_PARTITION 1
174#endif
175
176/*----------------------------------------------------------------------------
177 * SMSC9115 Ethernet from SMSC9118 family
178 *----------------------------------------------------------------------------
179 */
180#if defined(CONFIG_CMD_NET)
181
Nishanth Menon03542c02009-10-16 00:06:36 -0500182#define CONFIG_LAN91C96
Tom Rixc5a51352009-10-17 12:41:06 -0500183#define CONFIG_LAN91C96_BASE DEBUG_BASE
184#define CONFIG_LAN91C96_EXT_PHY
185
186#define CONFIG_BOOTP_SEND_HOSTNAME
187/*
188 * BOOTP fields
189 */
190#define CONFIG_BOOTP_SUBNETMASK 0x00000001
191#define CONFIG_BOOTP_GATEWAY 0x00000002
192#define CONFIG_BOOTP_HOSTNAME 0x00000004
193#define CONFIG_BOOTP_BOOTPATH 0x00000010
194#endif /* (CONFIG_CMD_NET) */
195
196/*
197 * Environment setup
198 *
199 * Default boot order: mmc bootscript, MMC uImage, NOR image.
200 * Network booting environment must be configured at site.
201 */
202
203/* allow overwriting serial config and ethaddr */
204#define CONFIG_ENV_OVERWRITE
205
206#define CONFIG_EXTRA_ENV_SETTINGS \
207 "loadaddr=0x82000000\0" \
208 "console=ttyS0,115200n8\0" \
209 "mmcargs=setenv bootargs console=${console} " \
210 "root=/dev/mmcblk0p2 rw " \
211 "rootfstype=ext3 rootwait\0" \
212 "norargs=setenv bootargs console=${console} " \
213 "root=/dev/mtdblock3 rw " \
214 "rootfstype=jffs2\0" \
215 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
216 "bootscript=echo Running bootscript from MMC/SD ...; " \
217 "autoscr ${loadaddr}\0" \
218 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
219 "mmcboot=echo Booting from MMC/SD ...; " \
220 "run mmcargs; " \
221 "bootm ${loadaddr}\0" \
222 "norboot=echo Booting from NOR ...; " \
223 "run norargs; " \
224 "bootm 0x80000\0" \
225
226#define CONFIG_BOOTCOMMAND \
227 "if mmcinit; then " \
228 "if run loadbootscript; then " \
229 "run bootscript; " \
230 "else " \
231 "if run loaduimage; then " \
232 "run mmcboot; " \
233 "else run norboot; " \
234 "fi; " \
235 "fi; " \
236 "else run norboot; fi"
237
238#define CONFIG_AUTO_COMPLETE 1
239
240/*--------------------------------------------------------------------------*/
241
242/*
243 * Miscellaneous configurable options
244 */
Tom Rixc5a51352009-10-17 12:41:06 -0500245
246#define CONFIG_SYS_LONGHELP /* undef to save memory */
247#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Robert P. J. Day23f5a2d2009-12-12 12:10:33 -0500248#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
Vaibhav Hiremathe1832902011-09-03 21:24:19 -0400249#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Tom Rixc5a51352009-10-17 12:41:06 -0500250/* Print Buffer Size */
251#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
252 sizeof(CONFIG_SYS_PROMPT) + 16)
253#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
254/* Boot Argument Buffer Size */
255#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
256
257/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
258 * a basic sanity check ONLY
259 * IF you would like to increase coverage, increase the end address
260 * or run the test with custom options
261 */
262#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
263#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
264
265/* Default load address */
266#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
267
268/*--------------------------------------------------------------------------*/
269
270/*
271 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
272 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
273 */
274#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
275#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Tom Rixc5a51352009-10-17 12:41:06 -0500276
Dirk Behmed834b012010-11-30 11:10:40 -0500277#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
278#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
279#define CONFIG_SYS_INIT_RAM_SIZE 0x800
280#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
281 CONFIG_SYS_INIT_RAM_SIZE - \
282 GENERATED_GBL_DATA_SIZE)
Tom Rixc5a51352009-10-17 12:41:06 -0500283/*
284 * SDRAM Memory Map
285 */
286#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
287#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Tom Rixc5a51352009-10-17 12:41:06 -0500288#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
289
Tom Rixc5a51352009-10-17 12:41:06 -0500290/*--------------------------------------------------------------------------*/
291
292/*
293 * NOR FLASH usage ... default nCS0:
294 * - one 256KB sector for U-Boot
295 * - one 256KB sector for its parameters (not all used)
296 * - eight sectors (2 MB) for kernel
297 * - rest for JFFS2
298 */
299
300/* Monitor at start of flash */
301#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
302#define CONFIG_SYS_MONITOR_LEN (256 << 10)
303
Tom Rixc5a51352009-10-17 12:41:06 -0500304/*
305 * NAND FLASH usage ... default nCS1:
306 * - four 128KB sectors for X-Loader
307 * - four 128KB sectors for U-Boot
308 * - two 128KB sector for its parameters
309 * - 32 sectors (4 MB) for kernel
310 * - rest for filesystem
311 */
312
313/*
314 * OneNAND FLASH usage ... default nCS2:
315 * - four 128KB sectors for X-Loader
316 * - two 128KB sectors for U-Boot
317 * - one 128KB sector for its parameters
318 * - sixteen sectors (2 MB) for kernel
319 * - rest for filesystem
320 */
321
Aneesh Vfa5c07a2011-11-21 23:38:59 +0000322#define CONFIG_SYS_CACHELINE_SIZE 64
323
Tom Rixc5a51352009-10-17 12:41:06 -0500324#endif /* __CONFIG_H */