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git01.mediatek.com / filogic / uboot / f53b5eada3ef08260ad704d4eb9a61063297e800 / . / include / power / max8997_pmic.h
blob: 728d60afa593b47bd93398b2184baa99222c2f41 [file] [log] [blame]
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Samsung Electronics
3 * Lukasz Majewski <l.majewski@samsung.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]6 */
7
8#ifndef __MAX8997_PMIC_H_
9#define __MAX8997_PMIC_H_
10
11/* MAX 8997 registers */
12enum {
13 MAX8997_REG_PMIC_ID0 = 0x00,
14 MAX8997_REG_PMIC_ID1 = 0x01,
15 MAX8997_REG_INTSRC = 0x02,
16 MAX8997_REG_INT1 = 0x03,
17 MAX8997_REG_INT2 = 0x04,
18 MAX8997_REG_INT3 = 0x05,
19 MAX8997_REG_INT4 = 0x06,
20
21 MAX8997_REG_INT1MSK = 0x08,
22 MAX8997_REG_INT2MSK = 0x09,
23 MAX8997_REG_INT3MSK = 0x0a,
24 MAX8997_REG_INT4MSK = 0x0b,
25
26 MAX8997_REG_STATUS1 = 0x0d,
27 MAX8997_REG_STATUS2 = 0x0e,
28 MAX8997_REG_STATUS3 = 0x0f,
29 MAX8997_REG_STATUS4 = 0x10,
30
31 MAX8997_REG_MAINCON1 = 0x13,
32 MAX8997_REG_MAINCON2 = 0x14,
33 MAX8997_REG_BUCKRAMP = 0x15,
34
35 MAX8997_REG_BUCK1CTRL = 0x18,
36 MAX8997_REG_BUCK1DVS1 = 0x19,
37 MAX8997_REG_BUCK1DVS2 = 0x1a,
38 MAX8997_REG_BUCK1DVS3 = 0x1b,
39 MAX8997_REG_BUCK1DVS4 = 0x1c,
40 MAX8997_REG_BUCK1DVS5 = 0x1d,
41 MAX8997_REG_BUCK1DVS6 = 0x1e,
42 MAX8997_REG_BUCK1DVS7 = 0x1f,
43 MAX8997_REG_BUCK1DVS8 = 0x20,
44 MAX8997_REG_BUCK2CTRL = 0x21,
45 MAX8997_REG_BUCK2DVS1 = 0x22,
46 MAX8997_REG_BUCK2DVS2 = 0x23,
47 MAX8997_REG_BUCK2DVS3 = 0x24,
48 MAX8997_REG_BUCK2DVS4 = 0x25,
49 MAX8997_REG_BUCK2DVS5 = 0x26,
50 MAX8997_REG_BUCK2DVS6 = 0x27,
51 MAX8997_REG_BUCK2DVS7 = 0x28,
52 MAX8997_REG_BUCK2DVS8 = 0x29,
53 MAX8997_REG_BUCK3CTRL = 0x2a,
54 MAX8997_REG_BUCK3DVS = 0x2b,
55 MAX8997_REG_BUCK4CTRL = 0x2c,
56 MAX8997_REG_BUCK4DVS = 0x2d,
57 MAX8997_REG_BUCK5CTRL = 0x2e,
58 MAX8997_REG_BUCK5DVS1 = 0x2f,
59 MAX8997_REG_BUCK5DVS2 = 0x30,
60 MAX8997_REG_BUCK5DVS3 = 0x31,
61 MAX8997_REG_BUCK5DVS4 = 0x32,
62 MAX8997_REG_BUCK5DVS5 = 0x33,
63 MAX8997_REG_BUCK5DVS6 = 0x34,
64 MAX8997_REG_BUCK5DVS7 = 0x35,
65 MAX8997_REG_BUCK5DVS8 = 0x36,
66 MAX8997_REG_BUCK6CTRL = 0x37,
67 MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
68 MAX8997_REG_BUCK7CTRL = 0x39,
69 MAX8997_REG_BUCK7DVS = 0x3a,
70 MAX8997_REG_LDO1CTRL = 0x3b,
71 MAX8997_REG_LDO2CTRL = 0x3c,
72 MAX8997_REG_LDO3CTRL = 0x3d,
73 MAX8997_REG_LDO4CTRL = 0x3e,
74 MAX8997_REG_LDO5CTRL = 0x3f,
75 MAX8997_REG_LDO6CTRL = 0x40,
76 MAX8997_REG_LDO7CTRL = 0x41,
77 MAX8997_REG_LDO8CTRL = 0x42,
78 MAX8997_REG_LDO9CTRL = 0x43,
79 MAX8997_REG_LDO10CTRL = 0x44,
80 MAX8997_REG_LDO11CTRL = 0x45,
81 MAX8997_REG_LDO12CTRL = 0x46,
82 MAX8997_REG_LDO13CTRL = 0x47,
83 MAX8997_REG_LDO14CTRL = 0x48,
84 MAX8997_REG_LDO15CTRL = 0x49,
85 MAX8997_REG_LDO16CTRL = 0x4a,
86 MAX8997_REG_LDO17CTRL = 0x4b,
87 MAX8997_REG_LDO18CTRL = 0x4c,
88 MAX8997_REG_LDO21CTRL = 0x4d,
89
90 MAX8997_REG_MBCCTRL1 = 0x50,
91 MAX8997_REG_MBCCTRL2 = 0x51,
92 MAX8997_REG_MBCCTRL3 = 0x52,
93 MAX8997_REG_MBCCTRL4 = 0x53,
94 MAX8997_REG_MBCCTRL5 = 0x54,
95 MAX8997_REG_MBCCTRL6 = 0x55,
96 MAX8997_REG_OTPCGHCVS = 0x56,
97
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]98 MAX8997_REG_SAFEOUTCTRL = 0x5a,
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]99
100 MAX8997_REG_LBCNFG1 = 0x5e,
101 MAX8997_REG_LBCNFG2 = 0x5f,
102 MAX8997_REG_BBCCTRL = 0x60,
103
104 MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */
105 MAX8997_REG_FLASH2_CUR = 0x64,
106 MAX8997_REG_MOVIE_CUR = 0x65,
107 MAX8997_REG_GSMB_CUR = 0x66,
108 MAX8997_REG_BOOST_CNTL = 0x67,
109 MAX8997_REG_LEN_CNTL = 0x68,
110 MAX8997_REG_FLASH_CNTL = 0x69,
111 MAX8997_REG_WDT_CNTL = 0x6a,
112 MAX8997_REG_MAXFLASH1 = 0x6b,
113 MAX8997_REG_MAXFLASH2 = 0x6c,
114 MAX8997_REG_FLASHSTATUS = 0x6d,
115 MAX8997_REG_FLASHSTATUSMASK = 0x6e,
116
117 MAX8997_REG_GPIOCNTL1 = 0x70,
118 MAX8997_REG_GPIOCNTL2 = 0x71,
119 MAX8997_REG_GPIOCNTL3 = 0x72,
120 MAX8997_REG_GPIOCNTL4 = 0x73,
121 MAX8997_REG_GPIOCNTL5 = 0x74,
122 MAX8997_REG_GPIOCNTL6 = 0x75,
123 MAX8997_REG_GPIOCNTL7 = 0x76,
124 MAX8997_REG_GPIOCNTL8 = 0x77,
125 MAX8997_REG_GPIOCNTL9 = 0x78,
126 MAX8997_REG_GPIOCNTL10 = 0x79,
127 MAX8997_REG_GPIOCNTL11 = 0x7a,
128 MAX8997_REG_GPIOCNTL12 = 0x7b,
129
130 MAX8997_REG_LDO1CONFIG = 0x80,
131 MAX8997_REG_LDO2CONFIG = 0x81,
132 MAX8997_REG_LDO3CONFIG = 0x82,
133 MAX8997_REG_LDO4CONFIG = 0x83,
134 MAX8997_REG_LDO5CONFIG = 0x84,
135 MAX8997_REG_LDO6CONFIG = 0x85,
136 MAX8997_REG_LDO7CONFIG = 0x86,
137 MAX8997_REG_LDO8CONFIG = 0x87,
138 MAX8997_REG_LDO9CONFIG = 0x88,
139 MAX8997_REG_LDO10CONFIG = 0x89,
140 MAX8997_REG_LDO11CONFIG = 0x8a,
141 MAX8997_REG_LDO12CONFIG = 0x8b,
142 MAX8997_REG_LDO13CONFIG = 0x8c,
143 MAX8997_REG_LDO14CONFIG = 0x8d,
144 MAX8997_REG_LDO15CONFIG = 0x8e,
145 MAX8997_REG_LDO16CONFIG = 0x8f,
146 MAX8997_REG_LDO17CONFIG = 0x90,
147 MAX8997_REG_LDO18CONFIG = 0x91,
148 MAX8997_REG_LDO21CONFIG = 0x92,
149
150 MAX8997_REG_DVSOKTIMER1 = 0x97,
151 MAX8997_REG_DVSOKTIMER2 = 0x98,
152 MAX8997_REG_DVSOKTIMER4 = 0x99,
153 MAX8997_REG_DVSOKTIMER5 = 0x9a,
154
155 PMIC_NUM_OF_REGS = 0x9b,
156};
157
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]158#define ACTDISSAFEO1 (1 << 4)
159#define ACTDISSAFEO2 (1 << 5)
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]160#define ENSAFEOUT1 (1 << 6)
161#define ENSAFEOUT2 (1 << 7)
162
Łukasz Majewskid72e0ae2012-11-13 03:22:05 +0000[diff] [blame]163#define ENBUCK (1 << 0)
164#define ACTIVE_DISCHARGE (1 << 3)
165#define GNSLCT (1 << 2)
166#define LDO_ADE (1 << 1)
167#define SAFEOUT_4_85V 0x00
168#define SAFEOUT_4_90V 0x01
169#define SAFEOUT_4_95V 0x02
170#define SAFEOUT_3_30V 0x03
171
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]172/* Charger */
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]173#define DETBAT (1 << 2)
174#define MBCICHFCSET (1 << 4)
175#define MBCHOSTEN (1 << 6)
176#define VCHGR_FC (1 << 7)
177
178#define CHARGER_MIN_CURRENT 200
179#define CHARGER_MAX_CURRENT 950
180#define CHARGER_CURRENT_RESOLUTION 50
181
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]182#define MAX8997_I2C_ADDR (0xCC >> 1)
183#define MAX8997_RTC_ADDR (0x0C >> 1)
184#define MAX8997_MUIC_ADDR (0x4A >> 1)
185#define MAX8997_FG_ADDR (0x6C >> 1)
186
187enum {
188 LDO_OFF = 0,
189 LDO_ON = 1,
190
191 DIS_LDO = (0x00 << 6),
192 EN_LDO = (0x3 << 6),
193};
194
Łukasz Majewski57e91112012-11-13 03:22:04 +0000[diff] [blame]195#define MAX8997_LDO_MAX_VAL 0x3F
196unsigned char max8997_reg_ldo(int uV);
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]197#endif /* __MAX8997_PMIC_H_ */