Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / f522bf513579e96964e556fcd0c03ab5c8ad1480 / . / arch / arm / dts / tegra20-paz00.dts
blob: 16381c3a4c78777e39812e205361797aee3d984b [file] [log] [blame]
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]4
5/ {
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]13 aliases {
14 usb0 = "/usb@c5008000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]15 sdhci0 = "/sdhci@c8000600";
16 sdhci1 = "/sdhci@c8000000";
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]17 };
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]23 host1x {
24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]34 serial@70006000 {
35 clock-frequency = < 216000000 >;
36 };
37
38 i2c@7000c000 {
39 status = "disabled";
40 };
41
42 i2c@7000c400 {
43 status = "disabled";
44 };
45
46 i2c@7000c500 {
47 status = "disabled";
48 };
49
50 i2c@7000d000 {
51 status = "disabled";
52 };
53
54 usb@c5000000 {
55 status = "disabled";
56 };
57
58 usb@c5004000 {
59 status = "disabled";
60 };
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]61
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]62 sdhci@c8000000 {
63 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]64 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
65 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
66 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]67 bus-width = <4>;
68 };
69
70 sdhci@c8000600 {
71 status = "okay";
72 bus-width = <8>;
73 };
74
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]75 lcd_panel: panel {
76 /* PAZ00 has 1024x600 */
77 clock = <54030000>;
78 xres = <1024>;
79 yres = <600>;
80 right-margin = <160>;
81 left-margin = <24>;
82 hsync-len = <136>;
83 upper-margin = <3>;
84 lower-margin = <61>;
85 vsync-len = <6>;
86 hsync-active-high;
87 nvidia,bits-per-pixel = <16>;
88 nvidia,pwm = <&pwm 0 0>;
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]89 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
90 GPIO_ACTIVE_HIGH>;
91 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
92 GPIO_ACTIVE_HIGH>;
93 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
94 GPIO_ACTIVE_HIGH>;
95 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
96 GPIO_ACTIVE_HIGH>;
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000[diff] [blame]97 nvidia,panel-timings = <400 4 203 17 15>;
98 };
Stephen Warren24bfee62012-05-21 10:04:37 +0000[diff] [blame]99};