blob: 19fc38157d94e45f7dc19c73f3d0b77fd5bcdec4 [file] [log] [blame]
Suman Anna7e0cfeb2022-05-25 13:38:46 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM625 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu {
9 mcu_pmx0: pinctrl@4084000 {
10 compatible = "pinctrl-single";
11 reg = <0x00 0x04084000 0x00 0x88>;
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
15 };
16
Nishanth Menone17596d2023-07-27 04:03:31 -050017 mcu_esm: esm@4100000 {
18 compatible = "ti,j721e-esm";
19 reg = <0x00 0x4100000 0x00 0x1000>;
20 ti,esm-pins = <0>, <1>, <2>, <85>;
21 };
22
23 /*
24 * The MCU domain timer interrupts are routed only to the ESM module,
25 * and not currently available for Linux. The MCU domain timers are
26 * of limited use without interrupts, and likely reserved by the ESM.
27 */
28 mcu_timer0: timer@4800000 {
29 compatible = "ti,am654-timer";
30 reg = <0x00 0x4800000 0x00 0x400>;
31 clocks = <&k3_clks 35 2>;
32 clock-names = "fck";
33 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
34 ti,timer-pwm;
35 status = "reserved";
36 };
37
38 mcu_timer1: timer@4810000 {
39 compatible = "ti,am654-timer";
40 reg = <0x00 0x4810000 0x00 0x400>;
41 clocks = <&k3_clks 48 2>;
42 clock-names = "fck";
43 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
44 ti,timer-pwm;
45 status = "reserved";
46 };
47
48 mcu_timer2: timer@4820000 {
49 compatible = "ti,am654-timer";
50 reg = <0x00 0x4820000 0x00 0x400>;
51 clocks = <&k3_clks 49 2>;
52 clock-names = "fck";
53 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
54 ti,timer-pwm;
55 status = "reserved";
56 };
57
58 mcu_timer3: timer@4830000 {
59 compatible = "ti,am654-timer";
60 reg = <0x00 0x4830000 0x00 0x400>;
61 clocks = <&k3_clks 50 2>;
62 clock-names = "fck";
63 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
64 ti,timer-pwm;
65 status = "reserved";
66 };
67
Suman Anna7e0cfeb2022-05-25 13:38:46 +053068 mcu_uart0: serial@4a00000 {
69 compatible = "ti,am64-uart", "ti,am654-uart";
70 reg = <0x00 0x04a00000 0x00 0x100>;
71 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
72 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
73 clocks = <&k3_clks 149 0>;
74 clock-names = "fclk";
Nishanth Menone17596d2023-07-27 04:03:31 -050075 status = "disabled";
Suman Anna7e0cfeb2022-05-25 13:38:46 +053076 };
77
78 mcu_i2c0: i2c@4900000 {
79 compatible = "ti,am64-i2c", "ti,omap4-i2c";
80 reg = <0x00 0x04900000 0x00 0x100>;
81 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
85 clocks = <&k3_clks 106 2>;
86 clock-names = "fck";
Nishanth Menone17596d2023-07-27 04:03:31 -050087 status = "disabled";
Suman Anna7e0cfeb2022-05-25 13:38:46 +053088 };
89
90 mcu_spi0: spi@4b00000 {
91 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
92 reg = <0x00 0x04b00000 0x00 0x400>;
93 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
97 clocks = <&k3_clks 147 0>;
Nishanth Menone17596d2023-07-27 04:03:31 -050098 status = "disabled";
Suman Anna7e0cfeb2022-05-25 13:38:46 +053099 };
100
101 mcu_spi1: spi@4b10000 {
102 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
103 reg = <0x00 0x04b10000 0x00 0x400>;
104 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
108 clocks = <&k3_clks 148 0>;
Nishanth Menone17596d2023-07-27 04:03:31 -0500109 status = "disabled";
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530110 };
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530111
112 mcu_gpio_intr: interrupt-controller@4210000 {
113 compatible = "ti,sci-intr";
114 reg = <0x00 0x04210000 0x00 0x200>;
115 ti,intr-trigger-type = <1>;
116 interrupt-controller;
117 interrupt-parent = <&gic500>;
118 #interrupt-cells = <1>;
119 ti,sci = <&dmsc>;
120 ti,sci-dev-id = <5>;
121 ti,interrupt-ranges = <0 104 4>;
122 };
123
124 mcu_gpio0: gpio@4201000 {
125 compatible = "ti,am64-gpio", "ti,keystone-gpio";
126 reg = <0x00 0x4201000 0x00 0x100>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-parent = <&mcu_gpio_intr>;
130 interrupts = <30>, <31>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 ti,ngpio = <24>;
134 ti,davinci-gpio-unbanked = <0>;
135 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
136 clocks = <&k3_clks 79 0>;
137 clock-names = "gpio";
138 };
Nishanth Menone17596d2023-07-27 04:03:31 -0500139
140 mcu_rti0: watchdog@4880000 {
141 compatible = "ti,j7-rti-wdt";
142 reg = <0x00 0x04880000 0x00 0x100>;
143 clocks = <&k3_clks 131 0>;
144 power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
145 assigned-clocks = <&k3_clks 131 0>;
146 assigned-clock-parents = <&k3_clks 131 2>;
147 /* Tightly coupled to M4F */
148 status = "reserved";
149 };
Suman Anna7e0cfeb2022-05-25 13:38:46 +0530150};