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git01.mediatek.com / filogic / uboot / f4df60515232c75472a43d1b5ba25f3724e74619 / . / board / sandburst / karef / u-boot.lds.debug
blob: c17c8b939bdca65b52395404ec1deca887553ca2 [file] [log] [blame]
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]1/*
2 * (C) Copyright 2002-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]7 */
8
9OUTPUT_ARCH(powerpc)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]10/* Do we need any of these for elf?
11 __DYNAMIC = 0; */
12SECTIONS
13{
14 /* Read-only sections, merged into text segment: */
15 . = + SIZEOF_HEADERS;
16 .interp : { *(.interp) }
17 .hash : { *(.hash) }
18 .dynsym : { *(.dynsym) }
19 .dynstr : { *(.dynstr) }
20 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]21 .rela.text : { *(.rela.text) }
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]22 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]23 .rela.data : { *(.rela.data) }
24 .rel.rodata : { *(.rel.rodata) }
25 .rela.rodata : { *(.rela.rodata) }
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]26 .rel.got : { *(.rel.got) }
27 .rela.got : { *(.rela.got) }
28 .rel.ctors : { *(.rel.ctors) }
29 .rela.ctors : { *(.rela.ctors) }
30 .rel.dtors : { *(.rel.dtors) }
31 .rela.dtors : { *(.rela.dtors) }
32 .rel.bss : { *(.rel.bss) }
33 .rela.bss : { *(.rela.bss) }
34 .rel.plt : { *(.rel.plt) }
35 .rela.plt : { *(.rela.plt) }
36 .init : { *(.init) }
37 .plt : { *(.plt) }
38 .text :
39 {
40 /* WARNING - the following is hand-optimized to fit within */
41 /* the sector layout of our flash chips! XXX FIXME XXX */
42
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]43 arch/powerpc/cpu/ppc4xx/start.o (.text)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]44 board/sandburst/karef/init.o (.text)
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]45 arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
46 arch/powerpc/cpu/ppc4xx/traps.o (.text)
47 arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
48 arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
49 arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
50 arch/powerpc/cpu/ppc4xx/speed.o (.text)
Ben Warren91375732008-11-09 21:29:23 -0800[diff] [blame]51 drivers/net/4xx_enet.o (.text)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]52 common/dlmalloc.o (.text)
Peter Tyser685b7f52010-04-12 22:28:05 -0500[diff] [blame]53 lib/crc32.o (.text)
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]54 arch/powerpc/lib/extable.o (.text)
Peter Tyser685b7f52010-04-12 22:28:05 -0500[diff] [blame]55 lib/zlib.o (.text)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]56
Jean-Christophe PLAGNIOL-VILLARD4436c1e2008-09-10 22:48:01 +0200[diff] [blame]57/* common/env_embedded.o(.text) */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]58
59 *(.text)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]60 *(.got1)
61 }
62 _etext = .;
63 PROVIDE (etext = .);
64 .rodata :
65 {
66 *(.rodata)
67 *(.rodata1)
68 *(.rodata.str1.4)
Wolfgang Denkaaa7c002005-12-12 16:06:05 +0100[diff] [blame]69 *(.eh_frame)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]70 }
71 .fini : { *(.fini) } =0
72 .ctors : { *(.ctors) }
73 .dtors : { *(.dtors) }
74
75 /* Read-write section, merged into data segment: */
76 . = (. + 0x0FFF) & 0xFFFFF000;
77 _erotext = .;
78 PROVIDE (erotext = .);
79 .reloc :
80 {
81 *(.got)
82 _GOT2_TABLE_ = .;
83 *(.got2)
84 _FIXUP_TABLE_ = .;
85 *(.fixup)
86 }
87 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
88 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
89
90 .data :
91 {
92 *(.data)
93 *(.data1)
94 *(.sdata)
95 *(.sdata2)
96 *(.dynamic)
97 CONSTRUCTORS
98 }
99 _edata = .;
100 PROVIDE (edata = .);
101
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]102
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]103 . = ALIGN(4);
104 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]105 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]106 }
107
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]108
109 __start___ex_table = .;
110 __ex_table : { *(__ex_table) }
111 __stop___ex_table = .;
112
113 . = ALIGN(256);
114 __init_begin = .;
115 .text.init : { *(.text.init) }
116 .data.init : { *(.data.init) }
117 . = ALIGN(256);
118 __init_end = .;
119
120 __bss_start = .;
121 .bss :
122 {
123 *(.sbss) *(.scommon)
124 *(.dynbss)
125 *(.bss)
126 *(COMMON)
127 }
Albert ARIBAUD0198f9d2013-03-30 00:19:53 +0000[diff] [blame]128 __bss_end = . ;
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]129 PROVIDE (end = .);
130}