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git01.mediatek.com / filogic / uboot / f4dd7612f6f06e31be926b3741882c9b49f79354 / . / arch / arm / cpu / arm720t / start.S
blob: 0bb3441fb8f9196c2eb192570b42c80f4e2934c3 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]1/*
2 * armboot - Startup Code for ARM720 CPU-core
3 *
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]8 */
9
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]10#include <asm-offsets.h>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]11#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]12
13/*
14 *************************************************************************
15 *
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]16 * Startup Code (reset vector)
17 *
wdenk927034e2004-02-08 19:38:38 +0000[diff] [blame]18 * do important init only if we don't start from RAM!
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]19 * relocate armboot to ram
20 * setup stack
21 * jump to second stage
22 *
23 *************************************************************************
24 */
25
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200[diff] [blame]26 .globl reset
Heiko Schochercad80e12010-09-17 13:10:52 +0200[diff] [blame]27
28reset:
29 /*
30 * set the cpu to SVC32 mode
31 */
32 mrs r0,cpsr
33 bic r0,r0,#0x1f
34 orr r0,r0,#0xd3
35 msr cpsr,r0
36
37 /*
38 * we do sys-critical inits only at reboot,
39 * not when booting from ram!
40 */
41#ifndef CONFIG_SKIP_LOWLEVEL_INIT
42 bl cpu_init_crit
43#endif
44
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]45 bl _main
Heiko Schochercad80e12010-09-17 13:10:52 +0200[diff] [blame]46
47/*------------------------------------------------------------------------------*/
48
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]49 .globl c_runtime_cpu_setup
50c_runtime_cpu_setup:
51
52 mov pc, lr
53
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]54/*
55 *************************************************************************
56 *
57 * CPU_init_critical registers
58 *
59 * setup important registers
60 * setup memory timing
61 *
62 *************************************************************************
63 */
64
Axel Lin89a8f7a2013-05-21 13:44:10 +0000[diff] [blame]65#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]66cpu_init_crit:
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]67
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200[diff] [blame]68 mov ip, lr
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]69 /*
70 * before relocating, we have to setup RAM timing
wdenk927034e2004-02-08 19:38:38 +0000[diff] [blame]71 * because memory timing is board-dependent, you will
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]72 * find a lowlevel_init.S in your board directory.
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]73 */
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]74 bl lowlevel_init
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]75 mov lr, ip
76
77 mov pc, lr
Axel Lin89a8f7a2013-05-21 13:44:10 +0000[diff] [blame]78#endif /* CONFIG_SKIP_LOWLEVEL_INIT */