Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / f4d27e9ce042ee0705a1e54143f822a372c1886d / . / include / configs / stv0991.h
blob: 7eadb6d421e5d67aee38246828b88ce762ae88e8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]2/*
Patrice Chotardcc551162017-10-23 09:53:59 +0200[diff] [blame]3 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]5 */
6
7#ifndef __CONFIG_STV0991_H
8#define __CONFIG_STV0991_H
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]9#define CFG_SYS_EXCEPTION_VECTORS_HIGH
Vikas Manocha32b9e712014-11-18 10:42:23 -0800[diff] [blame]10
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]11/* ram memory-related information */
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]12#define PHYS_SDRAM_1 0x00000000
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]13#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]14#define PHYS_SDRAM_1_SIZE 0x00198000
15
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]16/* user interface */
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]17
18/* MISC */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]19#define CFG_SYS_INIT_RAM_SIZE 0x8000
20#define CFG_SYS_INIT_RAM_ADDR 0x00190000
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame]21/* U-Boot Load Address */
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]22
Vikas Manocha7f34a692014-11-18 10:42:24 -0800[diff] [blame]23/* Misc configuration */
Vikas Manocha7f34a692014-11-18 10:42:24 -0800[diff] [blame]24
Vikas Manocha33913c52014-11-18 10:42:22 -0800[diff] [blame]25#endif /* __CONFIG_H */