Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. |
| 4 | * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
| 5 | * |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | /* |
| 12 | * High Level Configuration Options |
| 13 | */ |
| 14 | #define CONFIG_E300 1 /* E300 family */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 15 | |
| 16 | /* |
| 17 | * On-board devices |
| 18 | * |
| 19 | * TSECs |
| 20 | */ |
| 21 | #define CONFIG_TSEC1 |
| 22 | #define CONFIG_TSEC2 |
| 23 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 24 | #define CONFIG_SYS_GPIO1_PRELIM |
| 25 | /* GPIO Default input/output settings */ |
| 26 | #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 |
| 27 | /* |
| 28 | * Default GPIO values: |
| 29 | * LED#1 enabled; WLAN enabled; Both COM LED on (orange) |
| 30 | */ |
| 31 | #define CONFIG_SYS_GPIO1_DAT 0x08008C00 |
| 32 | |
| 33 | /* |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 34 | * SERDES |
| 35 | */ |
| 36 | #define CONFIG_FSL_SERDES |
| 37 | #define CONFIG_FSL_SERDES1 0xe3000 |
| 38 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 39 | /* |
| 40 | * DDR Setup |
| 41 | */ |
Mario Six | c9f9277 | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 42 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 43 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
| 44 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
| 45 | | DDRCDR_PZ_LOZ \ |
| 46 | | DDRCDR_NZ_LOZ \ |
| 47 | | DDRCDR_ODT \ |
| 48 | | DDRCDR_Q_DRN) |
| 49 | /* 0x7b880001 */ |
| 50 | /* |
| 51 | * Manually set up DDR parameters |
| 52 | * consist of two chips HY5PS12621BFP-C4 from HYNIX |
| 53 | */ |
| 54 | |
| 55 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
| 56 | |
| 57 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 |
| 58 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
Joe Hershberger | cc03b80 | 2011-10-11 23:57:29 -0500 | [diff] [blame] | 59 | | CSCONFIG_ODT_RD_NEVER \ |
| 60 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ |
| 61 | | CSCONFIG_ROW_BIT_13 \ |
| 62 | | CSCONFIG_COL_BIT_10) |
| 63 | /* 0x80010102 */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 64 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 65 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
| 66 | | (0 << TIMING_CFG0_WRT_SHIFT) \ |
| 67 | | (0 << TIMING_CFG0_RRT_SHIFT) \ |
| 68 | | (0 << TIMING_CFG0_WWT_SHIFT) \ |
| 69 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ |
| 70 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ |
| 71 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ |
| 72 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) |
| 73 | /* 0x00220802 */ |
| 74 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
| 75 | | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ |
| 76 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ |
| 77 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ |
| 78 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ |
| 79 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ |
| 80 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ |
| 81 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) |
| 82 | /* 0x27256222 */ |
| 83 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
| 84 | | (4 << TIMING_CFG2_CPO_SHIFT) \ |
| 85 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ |
| 86 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ |
| 87 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ |
| 88 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ |
| 89 | | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) |
| 90 | /* 0x121048c5 */ |
| 91 | #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
| 92 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) |
| 93 | /* 0x03600100 */ |
| 94 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
| 95 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
Joe Hershberger | cc03b80 | 2011-10-11 23:57:29 -0500 | [diff] [blame] | 96 | | SDRAM_CFG_DBW_32) |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 97 | /* 0x43080000 */ |
| 98 | |
| 99 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
| 100 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
| 101 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) |
| 102 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
| 103 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
| 104 | |
| 105 | /* |
| 106 | * Memory test |
| 107 | */ |
| 108 | #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ |
| 109 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 |
| 110 | |
| 111 | /* |
| 112 | * The reserved memory |
| 113 | */ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 115 | |
| 116 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
| 117 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
| 118 | |
| 119 | /* |
| 120 | * Initial RAM Base Address Setup |
| 121 | */ |
| 122 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 123 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
Joe Hershberger | 49b7754 | 2011-10-11 23:57:24 -0500 | [diff] [blame] | 124 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 125 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 126 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 127 | |
| 128 | /* |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 129 | * FLASH on the Local Bus |
| 130 | */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 132 | |
| 133 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ |
| 134 | #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 135 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 136 | |
| 137 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 138 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
| 139 | |
| 140 | /* Flash Erase Timeout (ms) */ |
| 141 | #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) |
| 142 | /* Flash Write Timeout (ms) */ |
| 143 | #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) |
| 144 | |
| 145 | /* |
| 146 | * SJA1000 CAN controller on Local Bus |
| 147 | */ |
Joe Hershberger | 49b7754 | 2011-10-11 23:57:24 -0500 | [diff] [blame] | 148 | #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 |
Mario Six | c1e29d9 | 2019-01-21 09:18:01 +0100 | [diff] [blame] | 149 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 150 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 151 | /* |
| 152 | * CPLD on Local Bus |
| 153 | */ |
Joe Hershberger | 49b7754 | 2011-10-11 23:57:24 -0500 | [diff] [blame] | 154 | #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 |
Mario Six | c1e29d9 | 2019-01-21 09:18:01 +0100 | [diff] [blame] | 155 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 156 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 157 | /* |
| 158 | * Serial Port |
| 159 | */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 160 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 161 | #define CONFIG_SYS_NS16550_SERIAL |
| 162 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 163 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 164 | |
| 165 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 166 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 167 | |
| 168 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
| 169 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) |
| 170 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 171 | /* I2C */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_I2C |
| 173 | #define CONFIG_SYS_I2C_FSL |
| 174 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 175 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 176 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 177 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 178 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 179 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 180 | |
| 181 | /* |
| 182 | * General PCI |
| 183 | * Addresses are mapped 1-1. |
| 184 | */ |
| 185 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
| 186 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 |
| 187 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 |
| 188 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 |
| 189 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 |
| 190 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 |
| 191 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 |
| 192 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 |
| 193 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 |
| 194 | |
| 195 | /* enable PCIE clock */ |
| 196 | #define CONFIG_SYS_SCCR_PCIEXP1CM 1 |
| 197 | |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 198 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 199 | #define CONFIG_PCIE |
| 200 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 201 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
| 202 | #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 |
| 203 | |
| 204 | /* |
| 205 | * TSEC |
| 206 | */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
| 208 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
| 209 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
| 210 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
| 211 | |
| 212 | /* |
| 213 | * TSEC ethernet configuration |
| 214 | */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 215 | #define CONFIG_TSEC1_NAME "eTSEC0" |
| 216 | #define CONFIG_TSEC2_NAME "eTSEC1" |
| 217 | #define TSEC1_PHY_ADDR 1 |
| 218 | #define TSEC2_PHY_ADDR 2 |
| 219 | #define TSEC1_PHYIDX 0 |
| 220 | #define TSEC2_PHYIDX 0 |
| 221 | #define TSEC1_FLAGS 0 |
| 222 | #define TSEC2_FLAGS 0 |
| 223 | |
| 224 | /* Options are: eTSEC[0-1] */ |
| 225 | #define CONFIG_ETHPRIME "eTSEC0" |
| 226 | |
| 227 | /* |
| 228 | * Environment |
| 229 | */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 230 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
| 231 | CONFIG_SYS_MONITOR_LEN) |
| 232 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 233 | #define CONFIG_ENV_SIZE 0x2000 |
| 234 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 235 | |
| 236 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 237 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 238 | |
| 239 | /* |
| 240 | * BOOTP options |
| 241 | */ |
| 242 | #define CONFIG_BOOTP_BOOTFILESIZE |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 243 | |
| 244 | /* |
| 245 | * Command line configuration. |
| 246 | */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 247 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 248 | /* |
| 249 | * Miscellaneous configurable options |
| 250 | */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 252 | |
| 253 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 254 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 255 | /* Boot Argument Buffer Size */ |
| 256 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 257 | |
| 258 | /* |
| 259 | * For booting Linux, the board info and command line data |
| 260 | * have to be in the first 8 MB of memory, since this is |
| 261 | * the maximum mapped by the Linux kernel during initialization. |
| 262 | */ |
Kim Phillips | 363429f | 2010-09-22 15:36:27 -0500 | [diff] [blame] | 263 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 264 | |
| 265 | /* |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 266 | * Environment Configuration |
| 267 | */ |
| 268 | |
| 269 | #define CONFIG_ENV_OVERWRITE |
| 270 | |
| 271 | #if defined(CONFIG_TSEC_ENET) |
| 272 | #define CONFIG_HAS_ETH0 |
| 273 | #define CONFIG_HAS_ETH1 |
| 274 | #endif |
| 275 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 276 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
| 277 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 278 | |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 279 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 280 | "netdev=eth0\0" \ |
| 281 | "consoledev=ttyS0\0" \ |
| 282 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 283 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 284 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 285 | "addip=setenv bootargs ${bootargs} " \ |
| 286 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 287 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 288 | "addtty=setenv bootargs ${bootargs}" \ |
| 289 | " console=${consoledev},${baudrate}\0" \ |
| 290 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
| 291 | "addmisc=setenv bootargs ${bootargs}\0" \ |
| 292 | "kernel_addr=FC0A0000\0" \ |
| 293 | "fdt_addr=FC2A0000\0" \ |
| 294 | "ramdisk_addr=FC2C0000\0" \ |
| 295 | "u-boot=mpc8308_p1m/u-boot.bin\0" \ |
| 296 | "kernel_addr_r=1000000\0" \ |
| 297 | "fdt_addr_r=C00000\0" \ |
| 298 | "hostname=mpc8308_p1m\0" \ |
| 299 | "bootfile=mpc8308_p1m/uImage\0" \ |
| 300 | "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ |
| 301 | "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ |
| 302 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
| 303 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
| 304 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ |
| 305 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
| 306 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ |
| 307 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
| 308 | "run nfsargs addip addtty addmtd addmisc;" \ |
| 309 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
| 310 | "bootcmd=run flash_self\0" \ |
| 311 | "load=tftp ${loadaddr} ${u-boot}\0" \ |
Marek Vasut | fd5ba89 | 2012-09-23 17:41:23 +0200 | [diff] [blame] | 312 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
| 313 | " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 314 | " +${filesize};cp.b ${fileaddr} " \ |
Marek Vasut | fd5ba89 | 2012-09-23 17:41:23 +0200 | [diff] [blame] | 315 | __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ |
Ilya Yanok | 622aa20 | 2010-09-17 23:41:50 +0200 | [diff] [blame] | 316 | "upd=run load update\0" \ |
| 317 | |
| 318 | #endif /* __CONFIG_H */ |