blob: fff4a184a02fd47922fe60b02436fe4ab69f3d90 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Max Filippov88574052016-08-07 08:53:00 +03002#
3# (C) Copyright 2016 Cadence Design Systems Inc.
Max Filippov88574052016-08-07 08:53:00 +03004
Kever Yang525ea472019-04-02 20:41:25 +08005obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
Mario Six82ef4ba2018-08-06 10:23:35 +02006obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
7obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
8obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
9obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
Michal Simek8a196af2018-07-13 11:04:56 +020010obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
Mario Six82ef4ba2018-08-06 10:23:35 +020011obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
Michal Simekd1c6d422018-07-13 17:00:13 +020012obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
Masahiro Yamada836c55d2017-04-14 11:10:24 +090013obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
Simon Goldschmidtbe366392019-07-15 21:47:53 +020014obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
Simon Goldschmidtebfb9fb2019-07-15 21:47:54 +020015obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
Andreas Dannenbergebc68792018-08-27 15:57:46 +053016obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
Álvaro Fernández Rojasaa19aaf2017-04-25 00:39:14 +020017obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
Álvaro Fernández Rojas0da081e2017-05-16 18:29:13 +020018obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
Simon Glassd22c1352019-09-25 08:11:24 -060019obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
Chris Zankel05d0c5d2016-08-10 18:36:48 +030020obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o