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git01.mediatek.com / filogic / uboot / f4bdf1b148414eb0e356a39d2d8c92a9d6de0017 / . / configs / hrcon_defconfig
blob: bfbe37262505265fdcebb4117d5699e4bd4c721e [file] [log] [blame]
Dirk Eibachf74a0272014-11-13 19:21:18 +0100[diff] [blame]1CONFIG_PPC=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0xFE000000
Siva Durga Prasad Paladugu809438d2016-07-29 15:31:47 +0530[diff] [blame]3CONFIG_IDENT_STRING=" hrcon 0.01"
Mario Sixd10f3182019-01-21 09:17:53 +0100[diff] [blame]4CONFIG_SYS_CLK_FREQ=33333333
Dirk Eibachf74a0272014-11-13 19:21:18 +0100[diff] [blame]5CONFIG_MPC83xx=y
6CONFIG_TARGET_HRCON=y
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]7CONFIG_SYSTEM_PLL_VCO_DIV_2=y
8CONFIG_SYSTEM_PLL_FACTOR_4_1=y
9CONFIG_CORE_PLL_RATIO_3_1=y
10CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
11CONFIG_TSEC1_MODE_RGMII=y
12CONFIG_TSEC2_MODE_RGMII=y
Mario Sixa861ea62019-01-21 09:17:57 +0100[diff] [blame]13CONFIG_BAT0=y
14CONFIG_BAT0_NAME="DDR"
15CONFIG_BAT0_BASE=0x00000000
16CONFIG_BAT0_LENGTH_128_MBYTES=y
17CONFIG_BAT0_ACCESS_RW=y
18CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
19CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
20CONFIG_BAT0_USER_MODE_VALID=y
21CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
22CONFIG_BAT1=y
23CONFIG_BAT1_NAME="IMMRBAR"
24CONFIG_BAT1_BASE=0xE0000000
25CONFIG_BAT1_LENGTH_8_MBYTES=y
26CONFIG_BAT1_ACCESS_RW=y
27CONFIG_BAT1_ICACHE_INHIBITED=y
28CONFIG_BAT1_ICACHE_GUARDED=y
29CONFIG_BAT1_DCACHE_INHIBITED=y
30CONFIG_BAT1_DCACHE_GUARDED=y
31CONFIG_BAT1_USER_MODE_VALID=y
32CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
33CONFIG_BAT2=y
34CONFIG_BAT2_NAME="FLASH"
35CONFIG_BAT2_BASE=0xFE000000
36CONFIG_BAT2_LENGTH_8_MBYTES=y
37CONFIG_BAT2_ACCESS_RW=y
38CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
39CONFIG_BAT2_DCACHE_INHIBITED=y
40CONFIG_BAT2_DCACHE_GUARDED=y
41CONFIG_BAT2_USER_MODE_VALID=y
42CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
43CONFIG_BAT3=y
44CONFIG_BAT3_NAME="STACK_IN_DCACHE"
45CONFIG_BAT3_BASE=0xE6000000
46CONFIG_BAT3_ACCESS_RW=y
47CONFIG_BAT3_USER_MODE_VALID=y
48CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
Mario Sixb47839c2019-01-21 09:17:58 +0100[diff] [blame]49CONFIG_LBLAW0=y
50CONFIG_LBLAW0_BASE=0xFE000000
51CONFIG_LBLAW0_NAME="FLASH"
52CONFIG_LBLAW0_LENGTH_8_MBYTES=y
53CONFIG_LBLAW1=y
54CONFIG_LBLAW1_BASE=0xE0600000
55CONFIG_LBLAW1_NAME="FPGA0"
56CONFIG_LBLAW1_LENGTH_1_MBYTES=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]57CONFIG_ELBC_BR0_OR0=y
58CONFIG_BR0_OR0_NAME="FLASH"
59CONFIG_BR0_OR0_BASE=0xFE000000
60CONFIG_BR0_PORTSIZE_16BIT=y
61CONFIG_OR0_AM_8_MBYTES=y
62CONFIG_OR0_XAM_SET=y
63CONFIG_OR0_SCY_15=y
64CONFIG_OR0_CSNT_EARLIER=y
65CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
66CONFIG_OR0_XACS_EXTENDED=y
67CONFIG_OR0_TRLX_RELAXED=y
68CONFIG_OR0_EHTR_8_CYCLE=y
69CONFIG_ELBC_BR1_OR1=y
70CONFIG_BR1_OR1_NAME="FPGA"
71CONFIG_BR1_OR1_BASE=0xE0600000
72CONFIG_BR1_PORTSIZE_16BIT=y
73CONFIG_OR1_AM_1_MBYTES=y
74CONFIG_OR1_XAM_SET=y
75CONFIG_OR1_SCY_15=y
76CONFIG_OR1_CSNT_EARLIER=y
77CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
78CONFIG_OR1_XACS_EXTENDED=y
79CONFIG_OR1_TRLX_RELAXED=y
80CONFIG_OR1_EHTR_8_CYCLE=y
Mario Six8b2141c2019-01-21 09:18:09 +0100[diff] [blame]81CONFIG_HID0_FINAL_EMCP=y
82CONFIG_HID0_FINAL_DPM=y
83CONFIG_HID0_FINAL_ICE=y
84CONFIG_HID2_HBE=y
Mario Six636c1082019-01-21 09:18:11 +0100[diff] [blame]85CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
Mario Six636c1082019-01-21 09:18:11 +0100[diff] [blame]86CONFIG_SICR_IEEE1588_A_GPIO=y
87CONFIG_SICR_GTM_GPIO=y
88CONFIG_SICR_ETSEC2_GPIO=y
89CONFIG_SICR_GPIOSEL_IEEE1588=y
90CONFIG_SICR_TMSOBI1_2_5_V=y
91CONFIG_SICR_TMSOBI2_2_5_V=y
Mario Sixaa502542019-01-21 09:18:12 +0100[diff] [blame]92CONFIG_ACR_PIPE_DEP_4=y
93CONFIG_ACR_RPTCNT_4=y
Mario Sixf62074e2019-01-21 09:18:13 +0100[diff] [blame]94CONFIG_SPCR_TSECEP_3=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]95CONFIG_LCRR_DBYP_PLL_BYPASSED=y
96CONFIG_LCRR_CLKDIV_2=y
Simon Glassec10c012017-05-17 03:25:35 -0600[diff] [blame]97CONFIG_CMD_IOLOOP=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]98CONFIG_FIT=y
99CONFIG_FIT_VERBOSE=y
100CONFIG_OF_BOARD_SETUP=y
101CONFIG_OF_STDOUT_VIA_ALIAS=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]102CONFIG_BOOTDELAY=5
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]103CONFIG_USE_PREBOOT=y
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]104CONFIG_SYS_CONSOLE_INFO_QUIET=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]105# CONFIG_DISPLAY_BOARDINFO is not set
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]106CONFIG_BOARD_EARLY_INIT_F=y
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]107CONFIG_BOARD_EARLY_INIT_R=y
Mario Six8febc7a2018-03-28 14:38:16 +0200[diff] [blame]108CONFIG_LAST_STAGE_INIT=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]109CONFIG_HUSH_PARSER=y
Stefan Roese83da3f12015-05-18 14:08:23 +0200[diff] [blame]110CONFIG_AUTOBOOT_KEYED=y
111CONFIG_AUTOBOOT_STOP_STR=" "
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]112CONFIG_CMD_IMLS=y
Simon Glass811eb262017-05-17 03:25:20 -0600[diff] [blame]113CONFIG_CMD_FPGAD=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]114CONFIG_CMD_I2C=y
115CONFIG_CMD_MMC=y
Simon Glassc88a09a2017-08-04 16:34:34 -0600[diff] [blame]116CONFIG_CMD_PCI=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]117# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]118CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]119CONFIG_CMD_PING=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]120CONFIG_CMD_EXT2=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]121CONFIG_DOS_PARTITION=y
Tom Rini4bb26a42019-11-10 11:28:03 -0500[diff] [blame]122CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]123CONFIG_FSL_ESDHC=y
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]124CONFIG_MTD_NOR_FLASH=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]125CONFIG_FLASH_CFI_DRIVER=y
126CONFIG_SYS_FLASH_PROTECTION=y
127CONFIG_SYS_FLASH_CFI=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]128CONFIG_PHY_MARVELL=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]129CONFIG_MII=y
Mario Sixda4fc932018-03-28 14:38:18 +0200[diff] [blame]130CONFIG_TSEC_ENET=y
Tom Rinie69ba982018-03-06 19:02:27 -0500[diff] [blame]131CONFIG_CONS_INDEX=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]132CONFIG_SYS_NS16550=y
Simon Glassa66c5412016-02-22 22:55:42 -0700[diff] [blame]133CONFIG_OF_LIBFDT=y