blob: fdb08f21115985924466463e8919edcef732109c [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -06007 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -07008
Simon Glassfef72b72014-07-23 06:55:03 -06009 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060011 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070012 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060013 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060014 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -070016 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060017 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070019 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070021 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -050022 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060024 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060026 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020027 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070028 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020034 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060038 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020041 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020042 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060043 };
44
Simon Glassed96cde2018-12-10 10:37:33 -070045 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -070050 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060051 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré9712c822019-10-07 15:29:05 +020079 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glassb2c1cac2014-02-26 15:59:21 -070083 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -060084 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070085 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -060086 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070087 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -060088 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -070089 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -070094 int-value = <1234>;
95 uint-value = <(-1234)>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070096 };
97
98 junk {
Simon Glasscf61f742015-07-06 12:54:36 -060099 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700100 compatible = "not,compatible";
101 };
102
103 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600104 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700105 };
106
Simon Glass5620cf82018-10-01 12:22:40 -0600107 backlight: backlight {
108 compatible = "pwm-backlight";
109 enable-gpios = <&gpio_a 1>;
110 power-supply = <&ldo_1>;
111 pwms = <&pwm 0 1000>;
112 default-brightness-level = <5>;
113 brightness-levels = <0 16 32 64 128 170 202 234 255>;
114 };
115
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200116 bind-test {
117 bind-test-child1 {
118 compatible = "sandbox,phy";
119 #phy-cells = <1>;
120 };
121
122 bind-test-child2 {
123 compatible = "simple-bus";
124 };
125 };
126
Simon Glassb2c1cac2014-02-26 15:59:21 -0700127 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600128 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700129 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600130 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700131 ping-add = <3>;
132 };
133
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200134 phy_provider0: gen_phy@0 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 phy_provider1: gen_phy@1 {
140 compatible = "sandbox,phy";
141 #phy-cells = <0>;
142 broken;
143 };
144
145 gen_phy_user: gen_phy_user {
146 compatible = "simple-bus";
147 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
148 phy-names = "phy1", "phy2", "phy3";
149 };
150
Simon Glassb2c1cac2014-02-26 15:59:21 -0700151 some-bus {
152 #address-cells = <1>;
153 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600154 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600155 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600156 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700157 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600158 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700159 compatible = "denx,u-boot-fdt-test";
160 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600161 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700162 ping-add = <5>;
163 };
Simon Glass40717422014-07-23 06:55:18 -0600164 c-test@0 {
165 compatible = "denx,u-boot-fdt-test";
166 reg = <0>;
167 ping-expect = <6>;
168 ping-add = <6>;
169 };
170 c-test@1 {
171 compatible = "denx,u-boot-fdt-test";
172 reg = <1>;
173 ping-expect = <7>;
174 ping-add = <7>;
175 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700176 };
177
178 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600179 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600180 ping-expect = <6>;
181 ping-add = <6>;
182 compatible = "google,another-fdt-test";
183 };
184
185 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600186 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600187 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700188 ping-add = <6>;
189 compatible = "google,another-fdt-test";
190 };
191
Simon Glass0ccb0972015-01-25 08:27:05 -0700192 f-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
196 g-test {
197 compatible = "denx,u-boot-fdt-test";
198 };
199
Bin Mengd9d24782018-10-10 22:07:01 -0700200 h-test {
201 compatible = "denx,u-boot-fdt-test1";
202 };
203
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200204 clocks {
205 clk_fixed: clk-fixed {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <1234>;
209 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000210
211 clk_fixed_factor: clk-fixed-factor {
212 compatible = "fixed-factor-clock";
213 #clock-cells = <0>;
214 clock-div = <3>;
215 clock-mult = <2>;
216 clocks = <&clk_fixed>;
217 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200218
219 osc {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <20000000>;
223 };
Stephen Warrena9622432016-06-17 09:44:00 -0600224 };
225
226 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600227 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600228 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200229 assigned-clocks = <&clk_sandbox 3>;
230 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600231 };
232
233 clk-test {
234 compatible = "sandbox,clk-test";
235 clocks = <&clk_fixed>,
236 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200237 <&clk_sandbox 0>,
238 <&clk_sandbox 3>,
239 <&clk_sandbox 2>;
240 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600241 };
242
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200243 ccf: clk-ccf {
244 compatible = "sandbox,clk-ccf";
245 };
246
Simon Glass5b968632015-05-22 15:42:15 -0600247 eth@10002000 {
248 compatible = "sandbox,eth";
249 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500250 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600251 };
252
253 eth_5: eth@10003000 {
254 compatible = "sandbox,eth";
255 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500256 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600257 };
258
Bin Meng04a11cb2015-08-27 22:25:53 -0700259 eth_3: sbe5 {
260 compatible = "sandbox,eth";
261 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500262 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700263 };
264
Simon Glass5b968632015-05-22 15:42:15 -0600265 eth@10004000 {
266 compatible = "sandbox,eth";
267 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500268 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600269 };
270
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700271 firmware {
272 sandbox_firmware: sandbox-firmware {
273 compatible = "sandbox,firmware";
274 };
275 };
276
Simon Glass25348a42014-10-13 23:42:11 -0600277 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700278 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700279 gpio-controller;
280 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700281 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700282 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700283 };
284
Simon Glass16e10402015-01-05 20:05:29 -0700285 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700286 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700287 gpio-controller;
288 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700289 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700290 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700291 };
Simon Glass25348a42014-10-13 23:42:11 -0600292
Simon Glass7df766e2014-12-10 08:55:55 -0700293 i2c@0 {
294 #address-cells = <1>;
295 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600296 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700297 compatible = "sandbox,i2c";
298 clock-frequency = <100000>;
299 eeprom@2c {
300 reg = <0x2c>;
301 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700302 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700303 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200304
Simon Glass336b2952015-05-22 15:42:17 -0600305 rtc_0: rtc@43 {
306 reg = <0x43>;
307 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700308 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600309 };
310
311 rtc_1: rtc@61 {
312 reg = <0x61>;
313 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700314 sandbox,emul = <&emul1>;
315 };
316
317 i2c_emul: emul {
318 reg = <0xff>;
319 compatible = "sandbox,i2c-emul-parent";
320 emul_eeprom: emul-eeprom {
321 compatible = "sandbox,i2c-eeprom";
322 sandbox,filename = "i2c.bin";
323 sandbox,size = <256>;
324 };
325 emul0: emul0 {
326 compatible = "sandbox,i2c-rtc";
327 };
328 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600329 compatible = "sandbox,i2c-rtc";
330 };
331 };
332
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200333 sandbox_pmic: sandbox_pmic {
334 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700335 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200336 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200337
338 mc34708: pmic@41 {
339 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700340 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200341 };
Simon Glass7df766e2014-12-10 08:55:55 -0700342 };
343
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100344 bootcount@0 {
345 compatible = "u-boot,bootcount-rtc";
346 rtc = <&rtc_1>;
347 offset = <0x13>;
348 };
349
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100350 adc@0 {
351 compatible = "sandbox,adc";
352 vdd-supply = <&buck2>;
353 vss-microvolts = <0>;
354 };
355
Simon Glass90b6fef2016-01-18 19:52:26 -0700356 lcd {
357 u-boot,dm-pre-reloc;
358 compatible = "sandbox,lcd-sdl";
359 xres = <1366>;
360 yres = <768>;
361 };
362
Simon Glassd783eb32015-07-06 12:54:34 -0600363 leds {
364 compatible = "gpio-leds";
365
366 iracibble {
367 gpios = <&gpio_a 1 0>;
368 label = "sandbox:red";
369 };
370
371 martinet {
372 gpios = <&gpio_a 2 0>;
373 label = "sandbox:green";
374 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200375
376 default_on {
377 gpios = <&gpio_a 5 0>;
378 label = "sandbox:default_on";
379 default-state = "on";
380 };
381
382 default_off {
383 gpios = <&gpio_a 6 0>;
384 label = "sandbox:default_off";
385 default-state = "off";
386 };
Simon Glassd783eb32015-07-06 12:54:34 -0600387 };
388
Stephen Warren62f2c902016-05-16 17:41:37 -0600389 mbox: mbox {
390 compatible = "sandbox,mbox";
391 #mbox-cells = <1>;
392 };
393
394 mbox-test {
395 compatible = "sandbox,mbox-test";
396 mboxes = <&mbox 100>, <&mbox 1>;
397 mbox-names = "other", "test";
398 };
399
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900400 cpus {
401 cpu-test1 {
402 compatible = "sandbox,cpu_sandbox";
403 u-boot,dm-pre-reloc;
404 };
Mario Sixdea5df72018-08-06 10:23:44 +0200405
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900406 cpu-test2 {
407 compatible = "sandbox,cpu_sandbox";
408 u-boot,dm-pre-reloc;
409 };
Mario Sixdea5df72018-08-06 10:23:44 +0200410
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900411 cpu-test3 {
412 compatible = "sandbox,cpu_sandbox";
413 u-boot,dm-pre-reloc;
414 };
Mario Sixdea5df72018-08-06 10:23:44 +0200415 };
416
Simon Glassc953aaf2018-12-10 10:37:34 -0700417 i2s: i2s {
418 compatible = "sandbox,i2s";
419 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700420 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700421 };
422
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200423 nop-test_0 {
424 compatible = "sandbox,nop_sandbox1";
425 nop-test_1 {
426 compatible = "sandbox,nop_sandbox2";
427 bind = "True";
428 };
429 nop-test_2 {
430 compatible = "sandbox,nop_sandbox2";
431 bind = "False";
432 };
433 };
434
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200435 misc-test {
436 compatible = "sandbox,misc_sandbox";
437 };
438
Simon Glasse4fef742017-04-23 20:02:07 -0600439 mmc2 {
440 compatible = "sandbox,mmc";
441 };
442
443 mmc1 {
444 compatible = "sandbox,mmc";
445 };
446
447 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600448 compatible = "sandbox,mmc";
449 };
450
Simon Glass53a68b32019-02-16 20:24:50 -0700451 pch {
452 compatible = "sandbox,pch";
453 };
454
Bin Meng408e5902018-08-03 01:14:41 -0700455 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700456 compatible = "sandbox,pci";
457 device_type = "pci";
458 #address-cells = <3>;
459 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600460 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700461 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700462 pci@0,0 {
463 compatible = "pci-generic";
464 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600465 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700466 };
Alex Margineanf1274432019-06-07 11:24:24 +0300467 pci@1,0 {
468 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600469 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
470 reg = <0x02000814 0 0 0 0
471 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600472 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300473 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700474 pci@1f,0 {
475 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600476 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
477 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600478 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700479 };
480 };
481
Simon Glassb98ba4c2019-09-25 08:56:10 -0600482 pci-emul0 {
483 compatible = "sandbox,pci-emul-parent";
484 swap_case_emul0_0: emul0@0,0 {
485 compatible = "sandbox,swap-case";
486 };
487 swap_case_emul0_1: emul0@1,0 {
488 compatible = "sandbox,swap-case";
489 use-ea;
490 };
491 swap_case_emul0_1f: emul0@1f,0 {
492 compatible = "sandbox,swap-case";
493 };
494 };
495
Bin Meng408e5902018-08-03 01:14:41 -0700496 pci1: pci-controller1 {
497 compatible = "sandbox,pci";
498 device_type = "pci";
499 #address-cells = <3>;
500 #size-cells = <2>;
501 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
502 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700503 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200504 0x0c 0x00 0x1234 0x5678
505 0x10 0x00 0x1234 0x5678>;
506 pci@10,0 {
507 reg = <0x8000 0 0 0 0>;
508 };
Bin Meng408e5902018-08-03 01:14:41 -0700509 };
510
Bin Meng510dddb2018-08-03 01:14:50 -0700511 pci2: pci-controller2 {
512 compatible = "sandbox,pci";
513 device_type = "pci";
514 #address-cells = <3>;
515 #size-cells = <2>;
516 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
517 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
518 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
519 pci@1f,0 {
520 compatible = "pci-generic";
521 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600522 sandbox,emul = <&swap_case_emul2_1f>;
523 };
524 };
525
526 pci-emul2 {
527 compatible = "sandbox,pci-emul-parent";
528 swap_case_emul2_1f: emul2@1f,0 {
529 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700530 };
531 };
532
Ramon Friedc64f19b2019-04-27 11:15:23 +0300533 pci_ep: pci_ep {
534 compatible = "sandbox,pci_ep";
535 };
536
Simon Glass9c433fe2017-04-23 20:10:44 -0600537 probing {
538 compatible = "simple-bus";
539 test1 {
540 compatible = "denx,u-boot-probe-test";
541 };
542
543 test2 {
544 compatible = "denx,u-boot-probe-test";
545 };
546
547 test3 {
548 compatible = "denx,u-boot-probe-test";
549 };
550
551 test4 {
552 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100553 first-syscon = <&syscon0>;
554 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100555 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600556 };
557 };
558
Stephen Warren92c67fa2016-07-13 13:45:31 -0600559 pwrdom: power-domain {
560 compatible = "sandbox,power-domain";
561 #power-domain-cells = <1>;
562 };
563
564 power-domain-test {
565 compatible = "sandbox,power-domain-test";
566 power-domains = <&pwrdom 2>;
567 };
568
Simon Glass5620cf82018-10-01 12:22:40 -0600569 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600570 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600571 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600572 };
573
574 pwm2 {
575 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600576 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600577 };
578
Simon Glass3d355e62015-07-06 12:54:31 -0600579 ram {
580 compatible = "sandbox,ram";
581 };
582
Simon Glassd860f222015-07-06 12:54:29 -0600583 reset@0 {
584 compatible = "sandbox,warm-reset";
585 };
586
587 reset@1 {
588 compatible = "sandbox,reset";
589 };
590
Stephen Warren6488e642016-06-17 09:43:59 -0600591 resetc: reset-ctl {
592 compatible = "sandbox,reset-ctl";
593 #reset-cells = <1>;
594 };
595
596 reset-ctl-test {
597 compatible = "sandbox,reset-ctl-test";
598 resets = <&resetc 100>, <&resetc 2>;
599 reset-names = "other", "test";
600 };
601
Nishanth Menonedf85812015-09-17 15:42:41 -0500602 rproc_1: rproc@1 {
603 compatible = "sandbox,test-processor";
604 remoteproc-name = "remoteproc-test-dev1";
605 };
606
607 rproc_2: rproc@2 {
608 compatible = "sandbox,test-processor";
609 internal-memory-mapped;
610 remoteproc-name = "remoteproc-test-dev2";
611 };
612
Simon Glass5620cf82018-10-01 12:22:40 -0600613 panel {
614 compatible = "simple-panel";
615 backlight = <&backlight 0 100>;
616 };
617
Ramon Fried26ed32e2018-07-02 02:57:59 +0300618 smem@0 {
619 compatible = "sandbox,smem";
620 };
621
Simon Glass76072ac2018-12-10 10:37:36 -0700622 sound {
623 compatible = "sandbox,sound";
624 cpu {
625 sound-dai = <&i2s 0>;
626 };
627
628 codec {
629 sound-dai = <&audio 0>;
630 };
631 };
632
Simon Glass25348a42014-10-13 23:42:11 -0600633 spi@0 {
634 #address-cells = <1>;
635 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600636 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600637 compatible = "sandbox,spi";
638 cs-gpios = <0>, <&gpio_a 0>;
639 spi.bin@0 {
640 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000641 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600642 spi-max-frequency = <40000000>;
643 sandbox,filename = "spi.bin";
644 };
645 };
646
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100647 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600648 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200649 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600650 };
651
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100652 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600653 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600654 reg = <0x20 5
655 0x28 6
656 0x30 7
657 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600658 };
659
Patrick Delaunayee010432019-03-07 09:57:13 +0100660 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900661 compatible = "simple-mfd", "syscon";
662 reg = <0x40 5
663 0x48 6
664 0x50 7
665 0x58 8>;
666 };
667
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800668 timer {
669 compatible = "sandbox,timer";
670 clock-frequency = <1000000>;
671 };
672
Miquel Raynal80938c12018-05-15 11:57:27 +0200673 tpm2 {
674 compatible = "sandbox,tpm2";
675 };
676
Simon Glass5b968632015-05-22 15:42:15 -0600677 uart0: serial {
678 compatible = "sandbox,serial";
679 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500680 };
681
Simon Glass31680482015-03-25 12:23:05 -0600682 usb_0: usb@0 {
683 compatible = "sandbox,usb";
684 status = "disabled";
685 hub {
686 compatible = "sandbox,usb-hub";
687 #address-cells = <1>;
688 #size-cells = <0>;
689 flash-stick {
690 reg = <0>;
691 compatible = "sandbox,usb-flash";
692 };
693 };
694 };
695
696 usb_1: usb@1 {
697 compatible = "sandbox,usb";
698 hub {
699 compatible = "usb-hub";
700 usb,device-class = <9>;
701 hub-emul {
702 compatible = "sandbox,usb-hub";
703 #address-cells = <1>;
704 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700705 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600706 reg = <0>;
707 compatible = "sandbox,usb-flash";
708 sandbox,filepath = "testflash.bin";
709 };
710
Simon Glass4700fe52015-11-08 23:48:01 -0700711 flash-stick@1 {
712 reg = <1>;
713 compatible = "sandbox,usb-flash";
714 sandbox,filepath = "testflash1.bin";
715 };
716
717 flash-stick@2 {
718 reg = <2>;
719 compatible = "sandbox,usb-flash";
720 sandbox,filepath = "testflash2.bin";
721 };
722
Simon Glassc0ccc722015-11-08 23:48:08 -0700723 keyb@3 {
724 reg = <3>;
725 compatible = "sandbox,usb-keyb";
726 };
727
Simon Glass31680482015-03-25 12:23:05 -0600728 };
729 };
730 };
731
732 usb_2: usb@2 {
733 compatible = "sandbox,usb";
734 status = "disabled";
735 };
736
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200737 spmi: spmi@0 {
738 compatible = "sandbox,spmi";
739 #address-cells = <0x1>;
740 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600741 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200742 pm8916@0 {
743 compatible = "qcom,spmi-pmic";
744 reg = <0x0 0x1>;
745 #address-cells = <0x1>;
746 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600747 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200748
749 spmi_gpios: gpios@c000 {
750 compatible = "qcom,pm8916-gpio";
751 reg = <0xc000 0x400>;
752 gpio-controller;
753 gpio-count = <4>;
754 #gpio-cells = <2>;
755 gpio-bank-name="spmi";
756 };
757 };
758 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700759
760 wdt0: wdt@0 {
761 compatible = "sandbox,wdt";
762 };
Rob Clarka471b672018-01-10 11:33:30 +0100763
Mario Six95922152018-08-09 14:51:19 +0200764 axi: axi@0 {
765 compatible = "sandbox,axi";
766 #address-cells = <0x1>;
767 #size-cells = <0x1>;
768 store@0 {
769 compatible = "sandbox,sandbox_store";
770 reg = <0x0 0x400>;
771 };
772 };
773
Rob Clarka471b672018-01-10 11:33:30 +0100774 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700775 #address-cells = <1>;
776 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100777 chosen-test {
778 compatible = "denx,u-boot-fdt-test";
779 reg = <9 1>;
780 };
781 };
Mario Six35616ef2018-03-12 14:53:33 +0100782
783 translation-test@8000 {
784 compatible = "simple-bus";
785 reg = <0x8000 0x4000>;
786
787 #address-cells = <0x2>;
788 #size-cells = <0x1>;
789
790 ranges = <0 0x0 0x8000 0x1000
791 1 0x100 0x9000 0x1000
792 2 0x200 0xA000 0x1000
793 3 0x300 0xB000 0x1000
794 >;
795
Fabien Dessenne22236e02019-05-31 15:11:30 +0200796 dma-ranges = <0 0x000 0x10000000 0x1000
797 1 0x100 0x20000000 0x1000
798 >;
799
Mario Six35616ef2018-03-12 14:53:33 +0100800 dev@0,0 {
801 compatible = "denx,u-boot-fdt-dummy";
802 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100803 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100804 };
805
806 dev@1,100 {
807 compatible = "denx,u-boot-fdt-dummy";
808 reg = <1 0x100 0x1000>;
809
810 };
811
812 dev@2,200 {
813 compatible = "denx,u-boot-fdt-dummy";
814 reg = <2 0x200 0x1000>;
815 };
816
817
818 noxlatebus@3,300 {
819 compatible = "simple-bus";
820 reg = <3 0x300 0x1000>;
821
822 #address-cells = <0x1>;
823 #size-cells = <0x0>;
824
825 dev@42 {
826 compatible = "denx,u-boot-fdt-dummy";
827 reg = <0x42>;
828 };
829 };
830 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200831
832 osd {
833 compatible = "sandbox,sandbox_osd";
834 };
Tom Rinib93eea72018-09-30 18:16:51 -0400835
Mario Sixab664ff2018-07-31 11:44:13 +0200836 board {
837 compatible = "sandbox,board_sandbox";
838 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200839
840 sandbox_tee {
841 compatible = "sandbox,tee";
842 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700843
844 sandbox_virtio1 {
845 compatible = "sandbox,virtio1";
846 };
847
848 sandbox_virtio2 {
849 compatible = "sandbox,virtio2";
850 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200851
852 pinctrl {
853 compatible = "sandbox,pinctrl";
854 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100855
856 hwspinlock@0 {
857 compatible = "sandbox,hwspinlock";
858 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100859
860 dma: dma {
861 compatible = "sandbox,dma";
862 #dma-cells = <1>;
863
864 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
865 dma-names = "m2m", "tx0", "rx0";
866 };
Alex Marginean0daa53a2019-06-03 19:12:28 +0300867
Alex Marginean0649be52019-07-12 10:13:53 +0300868 /*
869 * keep mdio-mux ahead of mdio so that the mux is removed first at the
870 * end of the test. If parent mdio is removed first, clean-up of the
871 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
872 * active at the end of the test. That it turn doesn't allow the mdio
873 * class to be destroyed, triggering an error.
874 */
875 mdio-mux-test {
876 compatible = "sandbox,mdio-mux";
877 #address-cells = <1>;
878 #size-cells = <0>;
879 mdio-parent-bus = <&mdio>;
880
881 mdio-ch-test@0 {
882 reg = <0>;
883 };
884 mdio-ch-test@1 {
885 reg = <1>;
886 };
887 };
888
889 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +0300890 compatible = "sandbox,mdio";
891 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700892};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200893
894#include "sandbox_pmic.dtsi"